Zhongying Xue

TCAD study on gate-all-around cylindrical (GAAC) transistor for CMOS scaling to the end of the roadmap

In this paper, we report TCAD study on gate-all-around cylindrical (GAAC) transistor for sub-10-nm scaling. The GAAC transistor device physics, TCAD simulation, and proposed fabrication procedure have been discussed. Among all other novel fin field effect transistor (FinFET) devices, the gate-all-around cylindrical device can be particularly used for reducing the problems of conventional multi-gate FinFET, improving device performance, and scaling-down capabilities. With gate-all-around cylindrical architecture, the transistor is controlled essentially by infinite number of gates surrounding the entire cylinder-shaped channel. Electrical integrity within the channel is improved by reducing the leakage current due to the non-symmetrical field accumulation such as the corner effect. Our proposed fabrication procedure for making devices having the gate-all-around cylindrical (GAAC) device architecture is also discussed.

Three dimensional strain distribution of wrinkled silicon nanomembranes fabricated by rolling-transfer technique

This paper introduces a simple transfer technique named as rolling-transfer technology to transfer Si nanomembranes to pre-stressed elastomers with nearly 100% transfer efficiency. When transferred onto the elastomeric substrate, wave-like wrinkled Si nanomembranes with uniform periodicity and amplitude are formed. The three dimensional (3-D) strain distribution of the wrinkled Si nanomembranes has been investigated in detail through the micro-Raman mapping using two excited laser wavelengths. The sinusoidal bulking geometry of Si nanomembrane results in a periodical strain alternation along x direction, while a homogenous strain distribution in y direction. The inhomogeneous strain distribution along z direction can be interpreted with the physical model considering the shift of the neutral mechanical plane, which is qualitatively determined by the Von Karman elastic nonlinear plate theory, including the bending effect and the shear forces existing at the Si nanomembrane/elastomeric substrate interface.

Deterministic Assembly of Flexible Si/Ge Nanoribbons via Edge-Cutting Transfer and Printing for van der Waals Heterojunctions

As the promising building blocks for flexible electronics and photonics, inorganic semiconductor nanomembranes have attracted considerable attention owing to their excellent mechanical flexibility and electrical/optical properties. To functionalize these building blocks with complex components, transfer and printing methods in a convenient and precise way are urgently demanded. A combined and controllable approach called edge-cutting transfer method to assemble semiconductor nanoribbons with defined width (down to submicrometer) and length (up to millimeter) is proposed. The transfer efficiency can be comprehended by a classical cantilever model, in which the difference of stress distributions between forth and back edges is investigated using finite element method. In addition, the vertical van der Waals PN (p-Si/n-Ge) junction constructed by a two-round process presents a typical rectifying behavior. The proposed technology may provide a practical, reliable, and cost-efficient strategy for transfer and printing routines, and thus expediting its potential applications for roll-to-roll productions for flexible devices.

Uniaxial and tensile strained germanium nanomembranes in rolled-up geometry by polarized Raman scattering spectroscopy

We present a rolled-up approach to form Ge microtubes and their array by rolling-up hybrid Ge/Cr nanomembranes, which is driven by the built-in stress in the deposited Cr layer. The study of Raman intensity as a function of the angle between the crystal-axis and the polarization-direction of the scattered light, i.e., polarized Raman measurement reveals that the strain state in Ge tube is uniaxial and tensile, and can reach a maximal value 1.0%. Both experimental observations and theoretical calculations suggest that the uniaxial-tensile strain residual in the rolled-up Ge tubes correlates with their tube diameters, which can be tuned by the thicknesses of the Cr layers deposited. Using the polarized Raman scattering spectroscopy, our study provides a comprehensive analysis of the strain state and evolution in self-rolled-up nano/micro-tubes.

Sharp crack formation in low fluence hydrogen implanted Si0.75Ge0.25/B doped Si0.70Ge0.30/Si heterostructure

An approach to transfer a high-quality SiGe layer for the fabrication of SiGe-on-insulator wafers has been proposed based on the investigation of crack formation in H-implanted Si0.75Ge0.25/B-doped Si0.70Ge0.30/Si structures. The crack formation is found to be closely correlated to the concentration of B atoms doped in the buried Si0.70Ge0.30 layer. For H-implanted Si0.75Ge0.25/Si0.70Ge0.30/Si structures without B doping, no platelets or cracking is observed in the Si0.70Ge0.30 layer. Upon increasing the concentration of B doping in the buried Si0.70Ge0.30 layer to 2 × 1019/cm3, cracking occurs at the interfaces on both sides of Si0.70Ge0.30 interlayer, thus, resulting in the formation of continuous sharp crack confined in the ultrathin Si0.70Ge0.30 interlayer. With B doped ultrathin Si0.70Ge0.30 interlayer, the Si0.75Ge0.25 layer can be transferred to fabricate SiGe-on-insulator by H implantation with a fluence as low as 3 × 1016/cm2, which is only half of the typical fluence required for a conventional ...

Germanium-Assisted Direct Growth of Graphene on Arbitrary Dielectric Substrates for Heating Devices

Direct growth of graphene on dielectric substrates is a prerequisite to the development of graphene-based electronic and optoelectronic devices. However, the current graphene synthesis methods on dielectric substrates always involve a metal contamination problem, and the direct production of graphene patterns still remains unattainable and challenging. Herein, a semiconducting, germanium (Ge)-assisted, chemical vapor deposition approach is proposed to produce monolayer graphene directly on arbitrary dielectric substrates. By the prepatterning of a catalytic Ge layer, the graphene with desired pattern can be achieved conveniently and readily. Due to the catalysis of Ge, monolayer graphene is able to form on Ge-covered dielectric substrates including SiO2 /Si, quartz glass, and sapphire substrates. Optimization of the process parameters leads to complete sublimation of the catalytic Ge layer during or immediately after formation of the monolayer graphene, enabling direct deposition of large-area and continuous graphene on dielectric substrates. The large-area, highly conductive graphene synthesized on a transparent dielectric substrate using the proposed approach has exhibited a wide range of applications, including in both defogger and thermochromic displays, as already successfully demonstrated here.

Strain redistribution in free-standing bridge structure released from strained silicon-on-insulator

The strain evolution including relaxation and conversion during the fabrication of free-standing bridge structure, which is the building block for the gate-all-around transistor, has been investigated in strained silicon-on-insulator. Compared to the starting strained silicon-on-insulator substrate, the strain of the free-standing bridge structure transforms from the biaxial strain to the uniaxial strain after patterning and release due to its unique configuration, as suggested by UV-Raman spectroscopy. Furthermore, such uniaxial strain has strong correlation with the dimension of the suspended structure, and it is enhanced as the width of the free-standing bridge decreases and the size of the connected pad increases. For 0.5μm-wide free-standing bridge connected to the pad of 16 × 16 μm2, the maximum uniaxial tensile strain of 4.65% is obtained, which remarkably exceeds the levels that can be achieved by other techniques ever reported. The observed strain redistribution phenomenon is also analyzed by two...

Manipulation of strain state in silicon nanoribbons by top-down approach

Tensile strain is often utilized to enhance the electron mobility and luminescent characteristics of semiconductors. A top-down approach in conjunction with roll-up technology is adopted to produce high tensile strain in Si nanoribbons by patterning and releasing of the bridge-like structures. The tensile strain can be altered between uniaxial state and biaxial state by adjusting the dimensions of the patterns and can be varied controllably up to 3.2% and 0.9% for the uniaxial- and biaxial-strained Si nanoribbons, respectively. Three-dimensional finite element analysis is performed to investigate the mechanism of strain generation during patterning and releasing of the structure. Since the process mainly depends on the geometrical factors, the technique can be readily extended to other types of mechanical, electrical, and optical membranes.

Fabrication of radiation hardened SOI with embedded Si nanocrystal by ion-cut technique

The ion-cut technique has been proposed to improve the top Si crystalline quality of the radiation hardened silicon-on-insulator (SOI). Si ion implantation prior to wafer bonding and splitting is performed to reduce the lattice damage induced by direct Si implantation through top Si film. Atomic-resolution transmission electron microscopy studies reveal that the top Si film possesses nearly perfect crystalline quality. Photoluminescence spectroscopy, x-ray photoelectron spectroscopy, and high-resolution transmission electron microscopy have corroborated the existence of the embedded Si nanocrystals. The pseudo-MOS transistors are fabricated on the hardened and unhardened SOI wafers for a quick and effective evaluation on the electrical properties of SOI wafers. The results indicate that the improvement in the total ionizing dose tolerance of the hardened SOI wafer can be attributed to the generation of deep electron and proton traps which reduce the positive charge build-up defects in the buried oxides.

High quality extremely thin SOI fabricated by facilitated ion-cut with H-trapping effect

High-quality strain-relaxed extremely thin silicon-on-insulator (ETSOI) has been fabricated by using H-trapping and etch-stop process in the H-implanted Si/Si0.70Ge0.30/Si/B-doped Si0.70Ge0.30/Si heterostructure. Compared to conventional ion-cut process, the combination of ultrathin SiGe interlayer with boron doping can significantly decrease the critical hydrogen implantation dosage needed for layer transfer by improving H-trapping efficiency. During subsequent annealing process, implanted H preferentially agglomerates at the trapping centers and induces long microcracks at the B-doped Si0.70Ge0.30/Si interface as well as in the near-interface region. The selective etch-stop process was used to remove residual Si/SiGe layers to expose a strain-relaxed Si device layer with a smooth surface morphology. These results demonstrate facilitated ion-cut as a promising approach for fabricating high crystalline quality ETSOI substrate and further offer a potential solution for scaling planar complementary metal–ox...