Deyuan Xiao

TCAD study on gate-all-around cylindrical (GAAC) transistor for CMOS scaling to the end of the roadmap

In this paper, we report TCAD study on gate-all-around cylindrical (GAAC) transistor for sub-10-nm scaling. The GAAC transistor device physics, TCAD simulation, and proposed fabrication procedure have been discussed. Among all other novel fin field effect transistor (FinFET) devices, the gate-all-around cylindrical device can be particularly used for reducing the problems of conventional multi-gate FinFET, improving device performance, and scaling-down capabilities. With gate-all-around cylindrical architecture, the transistor is controlled essentially by infinite number of gates surrounding the entire cylinder-shaped channel. Electrical integrity within the channel is improved by reducing the leakage current due to the non-symmetrical field accumulation such as the corner effect. Our proposed fabrication procedure for making devices having the gate-all-around cylindrical (GAAC) device architecture is also discussed.

Device Simulation on Gate-All-Around Cylindrical Transistor

In this paper, we reported TCAD study on gate-all-around cylindrical (GAAC) transistor for sub-10 nm scaling. The GAAC transistor device physics, TCAD simulation have been discussed. Among all other novel FinFET devices, the gate-all-around cylindrical device can be particularly applied for reducing the problems of the conventional multi-gate FinFET and improving the device performance and the scale down capability.

A Novel Accumulation Mode GAAC FinFET Transistor: Device Analysis, 3D TCAD Simulation and Fabrication

We report the analysis and TCAD results on gate-all-around cylindrical (GAAC) FinFETs with operation based on channel accumulation. GAAC FinFETs operating in accumulation mode in which the current in accumulation is flowing across the whole cylinder-shaped Si body, have high mobility, reduced lowfrequency noise and short-channel effects, increased the threshold voltage and avoid effects due to depletion of poly-Si gates. The Ion/Ioff ratio of the device can be larger than 10 6 , a key parameter for device operation.