Zhou Duan

A full asynchronous serial transmission converter for network-on-chips

Large transmission power consumptions and excessive interconnection lines are two shortcomings which exist in conventional network-on-chips. To improve performance in these areas, this paper proposes a full asynchronous serial transmission converter for network-on-chips. By grouping the parallel data between routers into smaller data blocks, interconnection lines between routers can be greatly reduced, which finally brings about saving of power overheads in the transmission process. Null convention logic units are used to make the circuit quasi-delay insensitive and highly robust. The proposed serial transmission converter and serial channel are implemented based on SMIC 0.18 μm standard CMOS technology. Results demonstrate that this full asynchronous serial transmission converter can save up to three quarters of the interconnection line resources and also reduce up to two-thirds of the power consumption under 32 bit data widths. The proposed full asynchronous serial transmission converter can apply to the on chip network which is sensitive to area and power.

A load balancing bufferless deflection router for network-on-chip*

The bufferless router emerges as an interesting option for cost-efficient in network-on-chip (NoC) design. However, the bufferless router only works well under low network load because deflection more easily occurs as the injection rate increases. In this paper, we propose a load balancing bufferless deflection router (LBBDR) for NoC that relieves the effect of deflection in bufferless NoC. The proposed LBBDR employs a balance toggle identifier in the source router to control the initial routing direction of X or Y for a flit in the network. Based on this mechanism, the flit is routed according to XY or YX routing in the network afterward. When two or more flits contend the same one desired output port a priority policy called nearer-first is used to address output ports allocation contention. Simulation results show that the proposed LBBDR yields an improvement of routing performance over the reported bufferless routing in the flit deflection rate, average packet latency and throughput by up to 13%, 10% and 6% respectively. The layout area and power consumption compared with the reported schemes are 12% and 7% less respectively.

Optimization design of a full asynchronous pipeline circuit based on null convention logic

This paper proposes a new optimization method to improve the performance of a null convention logic asynchronous pipeline. Parallel combinational logic modules in the pipelines can work alternately in null and data cycles by using a parallel processing mode. The complete waiting time for both null and data signals of combinational logic output in previous asynchronous register stage is reduced by decoupling the output from combinational logic modules. Performance penalty brought by null cycle is reduced while the data processing capacity is increased. The novel asynchronous pipeline based on asynchronous full adders with different bit widths as asynchronous combination logic modules is simulated using 0.18-μm CMOS technology. Based on 6 bits asynchronous adder as asynchronous combination logic modules, the simulation result of this new pipeline proposal demonstrates a high throughput up to 72.4% improvement with appropriate power consumption. This indicates the new design proposal is preferable for high-speed asynchronous designs due to its high throughput and delay-insensitivity.

A novel Monte-Carlo method for FPGA architecture research

A new Monte-Carlo-based approach is proposed for FPGA architecture research. Uniform open faults are randomly produced in the routing resource; and then interconnections are routed around obstacles. It does not depend on CAD algorithms and benchmark circuits. An example of switch block topology evaluation shows one can capture the same conclusion as that of CAD methods and shorten run-time from 15 hours to 15 minutes.

A self-adaptive full asynchronous bi-directional transmission channel for network-on-chips

To improve two shortcomings of conventional network-on-chips, i.e. low utilization rate in channels be- tween routers and excessive interconnection lines, this paper proposes a full asynchronous self-adaptive bi-directional transmission channel. It can utilize interconnection lines and register resources with high efficiency, and dynamically detect the data transmission state between routers through a direction regulator, which controls the sequencer to au- tomatically adjust the transmission direction of the bi-directional channel, so as to provide a flexible data transmis- sion environment. Null convention logic units are used to make the circuit quasi-delay insensitive and highly robust. The proposed bi-directional transmission channel is implemented based on SMIC 0.18 m standard CMOS technol- ogy. Post-layout simulation results demonstrate that this self-adaptive bi-directional channel has better performance on throughput, transmission flexibility and channel bandwidth utilization compared to a conventional single direction channel. Moreover, the proposed channel can save interconnection lines up to 30% and can provide twice the bandwidth resources of a single direction transmission channel. The proposed channel can apply to an on-chip network which has limited resources of registers and interconnection lines.