Zhuoyuan Li

Integrating dynamic thermal via planning with 3D floorplanning algorithm

Incorporating thermal vias into 3D ICs is a promising way to reduce circuit temperature by lowering down the thermal resistances between device layers. In this paper, we integrate dynamic thermal via planning into 3D floorplanning process. Our 3D floorplanning and thermal via planning approaches are implemented in a two-stage approach. Before floorplanning, the temperature-constrained vertical thermal via planning is formulated as a convex programming problem. Based on the analytical solution, blocks are assigned into different layers by solving a sequence of knapsack problems. Then a SA engine is used to generate floorplans of all these layers simultaneously. During floorplanning, thermal vias are distributed horizontally in each layer with white space redistribution to optimize thermal via insertion. Experimental results show that compared to a recent published result from [14], our method can reduce thermal vias by 15% with 38% runtime overhead.

Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization

Three-dimensional (3-D) IC physical design problems are usually of higher complexity, with a greatly enlarged solution space due to multiple device structure. In this paper, a new 3-D floorplanning algorithm is proposed for wirelength optimization. Our main contributions and results can be summarized as follows. First, a new hierarchical flow of 3-D floorplanning with a new inter-layer partitioning method. The blocks are partitioned into different layers before floorplanning. A simulated annealing (SA) engine is used to partition blocks with the objective of minimizing the statistical wirelength estimation results. The solution quality is not degraded by the hierarchical flow. Second, floorplans of all the layers are generated in a SA process. Original 3-D floorplanning problem is transformed into solving several 2-D floorplanning problems simultaneously. The solution space is scaled down to maintain a low design complexity. Finally, Experimental results show that our algorithm improves wirelength by 14%-51% compared with previous 3-D floorplanning algorithms. The hierarchical approach is proven to be very efficient and offers a potential way for high-performance 3-D design

Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration

New three-dimensional (3D) floorplanning and thermal via planning algorithms are proposed for thermal optimization in two-stacked die integration. Our contributions include (1) a two-stage design flow for 3D floorplanning, which scales down the enlarged solution space due to multidevice layer structure; (2) an efficient thermal-driven 3D floorplanning algorithm with power distribution constraints; (3) a thermal via planning algorithm considering congestion minimization. Experiments results show that our approach is nine times faster with better solution quality compared to a recent published result. In addition, the thermal via planning approach is proven to be very efficient to eliminate localized hot spots directly.

Congestion driven incremental placement algorithm for standard cell layout

Congestion minimization is the least understood in placement objectives, however, it models routability most accurately. In this paper, a new incremental placement algorithm C-ECOP for standard cell layout is presented to reduce routing congestion. Congestion estimation is based on a new routing model and a more accurate cost function. An integer linear programming (ILP) problem is formulated to determine cell flow direction and avoid the conflictions between adjacent congestion areas. Experimental results show that the algorithm can considerably reduce routing congestion and preserve the performance of the initial placement with high speed.

Via assignment algorithm for hierarchical 3D placement

Three-dimensional (3D) packaging technologies are now emerging to alleviate the interconnect delay problem, increase transistor packing density and reduce chip area. In 3D integration, vertical vias are utilized to realize interconnections between stacked layers. Route planning for these vertical wires by via assignment are of great importance for wirelength reduction, congestion alleviation and thermal optimization. Different via assignment algorithms are proposed for wirelength optimization. These methods are integrated in a hierarchical 3D design flow for mixed-mode placement (MMP). The experimental results show that total wirelength can be reduced by 8% with sacrifice on the runtime. Our algorithms are proved to be very effective and efficient.

A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation

An efficient and effective divide-and conquer 2.5D floorplanning algorithm is proposed for wirelength optimization. Modules are pre-partitioned into different dies with respect to the statistical wirelength estimation result. Then a floorplan is generated on each die for wirelength optimization. The new partitioning method successfully solves the conflict between wirelength minimization and inter-die via constraints. Experimental results show that our algorithm could provide noticeable improvement in the total wirelength compared to both 2D design and the previous 2.5D floorplanning algorithm.

Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning

For modern processor designs in nanometer technologies, both block and interconnect pipelining are needed to achieve multi-gigahertz clock frequency, but previous approaches consider block pipelining and interconnect pipelining separately. For example, all recent works on wire pipelining assume pre-pipelined components and consider only inserting pipeline stages on point-to-point wire or bus connections. To the best of our knowledge, this paper is the first that considers block pipelining and interconnect pipelining simultaneously. We optimize multiple critical paths or loops in the micro-architecture and insert the pipelines stages optimally in the blocks and wires of these loops to meet the clock frequency requirement. We propose two approaches to this problem. The first approach is based on mixed integer linear programming (MILP) which is theoretically guaranteed to produce the optimal solution, and the second one is an efficient graph-based algorithm that produces near-optimal solutions. Experimental results show that simultaneous block and interconnect pipelining leads to more than 20% improvement over wire-pipelining alone on the overall processor performance. Moreover, the graph-based approach gives solutions very close to the MILP results ( 2% more than MILP results on average) but in a much shorter runtime.

3D placement algorithm considering vertical channels and guided by 2D placement solution

3D integration is a potential solution to solve complex problem caused by interconnect delay that dominates the total budgets. In this placer, we bring up a 3D placement algorithm and focus on two issues: the effect of vertical channels and the constraint that cells can not leave the plane after assigned to it. Firstly, we develop an algorithm to verify the effect of vertical channels in wire length optimization. Secondly, because of the constraint presented above the placement quality is restricted badly. We research the possibility of improving placement quality by importing an initial solution. Experiments on a set of benchmarks prove our algorithm efficient and effective.

VFGR: A very fast parallel global router with accurate congestion modeling

With the rapid growth of design size and complexity, global routing has always been a hard problem. Several new factors contribute to global routing congestion and can only be measured and optimized in 3-D global routing rather than 2-D routing. We propose an enhanced congestion model in global routing to capture local congestion and more accurately reflect modern design rule requirements. To achieve better global and detailed routing solution quality, we propose a 3-D global router VFGR with parallel computing using this congestion model. Experimental results show that VFGR can achieve comparable or better global routing solution quality with two start-of-the-art global routers in shorter runtime. It is also demonstrated that adopting proposed congestion model in global routing, higher solution quality and much shorter runtime can be achieved in detailed routing stage.

Incremental Placement Algorithm for Multi-objective Optimization

A new incremental placement approach is described in this paper. The obtained timing information drives an efficient net-based placement technique, which dynamically adapts the net weights during successive placement steps. Several methods to combine timing optimization and congestion reducing together are proposed to achieve good result without increasing the computational load. Cells on critical paths are replaced according to timing and congestion constraints. Experimental results show that our approach can efficiently reduce cycle time and enhance route ability. The max path delay is reduced about 13% on an average after incremental placement on wirelength optimized circuits.A new incremental placement approach is described in this paper. The obtained timing information drives an efficient net-based placement technique, which dynamically adapts the net weights during successive placement steps. Several methods to combine timing optimization and congestion reducing together are proposed to achieve good result without increasing the computational load. Cells on critical paths are replaced according to timing and congestion constraints. Experimental results show that our approach can efficiently reduce cycle time and enhance route ability. The max path delay is reduced about 13% on an average after incremental placement on wirelength optimized circuits.