Kin Leong Pey

Dielectric breakdown mechanisms in gate oxides

In this paper we review the subject of oxide breakdown (BD), focusing our attention on the case of the gate dielectrics of interest for current Si microelectronics, i.e., Si oxides or oxynitrides of thickness ranging from some tens of nanometers down to about 1nm. The first part of the paper is devoted to a concise description of the subject concerning the kinetics of oxide degradation under high-voltage stress and the statistics of the time to BD. It is shown that, according to the present understanding, the BD event is due to a buildup in the oxide bulk of defects produced by the stress at high voltage. Defect concentration increases up to a critical value corresponding to the onset of one percolation path joining the gate and substrate across the oxide. This triggers the BD, which is therefore believed to be an intrinsic effect, not due to preexisting, extrinsic defects or processing errors. We next focus our attention on experimental studies concerning the kinetics of the final event of BD, during whi...

New salicidation technology with Ni(Pt) alloy for MOSFETs

A novel salicide technology to improve the thermal stability of the conventional Ni silicide has been developed by employing Ni(Pt) alloy salicidation. This technique provides an effective avenue to overcome the low thermal budget (<700/spl deg/C) of the conventional Ni salicidation by forming Ni(Pt)Si. The addition of Pt has enhanced the thermal stability of NiSi. Improved sheet resistance of the salicided narrow poly-Si and active lines was achieved up to 750/spl deg/C and 700/spl deg/C for as-deposited Ni(Pt) thickness of 30 nm and 15 nm, respectively. This successfully extends the rapid thermal processing (RTP) window by delaying the nucleation of NiSi/sub 2/ and agglomeration. Implementation of Ni(Pt) alloyed silicidation was demonstrated on PMOSFETs with high drive current and low junction leakage.

Effect of Copper TSV Annealing on Via Protrusion for TSV Wafer Fabrication

Three-dimensional (3D) integrated circuit (IC) technologies are receiving increasing attention due to their capability to enhance microchip function and performance. While current efforts are focused on the 3D process development, adequate reliability of copper (Cu) through-silicon vias (TSVs) is essential for commercial high-volume manufacturing. Annealing a silicon device with copper TSVs causes high stresses in the copper and may cause a “pumping” phenomenon in which copper is forced out of the blind TSV to form a protrusion. This is a potential threat to the back-end interconnect structure, particularly for low-κ materials, since it can lead to cracking or delamination. In this work, we studied the phenomenon of Cu protrusion and microstructural changes during thermal annealing of a TSV wafer. The extruded Cu-TSV was observed using scanning electron microscopy (SEM), 3D profilometry, and atomic force microscopy (AFM). The electron backscatter diffraction (EBSD) technique was employed to study the grain orientation of Cu-TSV and evolution of the grain size as a function of annealing temperature. The elastic modulus and yield stress of copper were characterized using nanoindentation. A model for Cu protrusion is proposed to provide insight into the failure mechanism. The results help to solve a key TSV-related manufacturing yield and reliability challenge by enabling high-throughput TSV fabrication for 3D IC integration.

Percolation path and dielectric-breakdown-induced-epitaxy evolution during ultrathin gate dielectric breakdown transient

A physical model has been developed which complies with the experimental observation on the failure mechanism of ultrathin gate oxide breakdown during constant voltage stress. Dynamic equilibrium needs to be established between the percolation conductive path and the dielectric breakdown induced epitaxy (DBIE) formation during gate dielectric breakdown transient. The model is capable of linking the percolation model, soft breakdown, and hard breakdown to the DBIE growth for a variety of stress conditions and gate oxide thickness without involving new empirical parameters.

Influence of Bosch Etch Process on Electrical Isolation of TSV Structures

Bosch process is widely used in the fabrication of through silicon via (TSV) holes for 3-D integrated circuit and 3-D Packaging applications mainly due to its high silicon etch rate and selectivity to mask. However, the adverse impact on the electrical performance of the TSV due to the sidewall scallops or wavy profile due to the cyclical nature of the Bosch process has not been thoroughly investigated. This paper therefore focuses on the impact of sidewall scallops on the inter-via electrical leakage performance. Based on finite element analysis, this paper describes that the high stress concentration on the dielectric and barrier layers at the sharp scallops can potentially contribute to barrier failure. It is demonstrated that by smoothening the sidewalls of the TSV, the thermo-mechanical stresses on the dielectric and tantalum barrier is significantly reduced. A test vehicle is designed and fabricated with different geometry of deep silicon vias to study the impact of sidewall profile smoothening for different copper diffusion barrier stacks. It is experimentally demonstrated that the inter-via electrical leakage current can be reduced by almost three orders of magnitude when the sidewall roughness is reduced or replaced by a smoother sidewall. It is also indicated that it is sufficient to smoothen the initial few micrometers of the TSV depth by using a non-Bosch etch process. It is concluded that the Bosch etch process can still be used, with all its merits of high etch rate and high etch selectivity, by tailoring a short initial etch step to smoothen the top sidewalls to minimize the adverse effects of the sidewall scallops.

Thermal reaction of nickel and Si0.75Ge0.25 alloy

The interfacial reactions and chemical phase formation between nickel and ultrahigh vacuum chemical vapor deposited Si0.75Ge0.25 alloy have been studied within the temperature range of 300–900 °C for forming low resistive and uniform silicide films for future application in SiGe based metal–oxide–semiconductor field effect transistor devices. The silicided films were characterized by the x-ray diffraction, Auger electron spectroscopy, scanning electron microscopy, transmission electron microscopy, and micro-Raman microscopy techniques. Smooth and uniform nickel monogermanosilicide NiSi0.75Ge0.25 films have been observed for samples annealed at around 400–500 °C. For annealing temperatures of 500 °C and above, Ge-rich Si1−zGez grains where z>0.25 were found among Ge deficient Niy(SiwGe1−w)1−y grains where w 0.25 were found among Ge deficient Niy(SiwGe1−w)1−y grains where w<0.25 and the Niy(Si1−wGew)1−y phase is thermally stable up to an annealing temperature of 800 °C. We found that the Ni/SiGe reaction is mainly diffusion controlled with Ge and Ni as the dominant diffusi...

Intrinsic nanofilamentation in resistive switching

Resistive switching materials are promising candidates for nonvolatile data storage and reconfiguration of electronic applications. Intensive studies have been carried out on sandwiched metal-insulator-metal structures to achieve high density on-chip circuitry and non-volatile memory storage. Here, we provide insight into the mechanisms that govern highly reproducible controlled resistive switching via a nanofilament by using an asymmetric metal-insulator-semiconductor structure. In-situ transmission electron microscopy is used to study in real-time the physical structure and analyze the chemical composition of the nanofilament dynamically during resistive switching. Electrical stressing using an external voltage was applied by a tungsten tip to the nanosized devices having hafnium oxide (HfO2) as the insulator layer. The formation and rupture of the nanofilaments result in up to three orders of magnitude change in the current flowing through the dielectric during the switching event. Oxygen vacancies and metal atoms from the anode constitute the chemistry of the nanofilament.Resistive switching materials are promising candidates for nonvolatile data storage and reconfiguration of electronic applications. Intensive studies have been carried out on sandwiched metal-insulator-metal structures to achieve high density on-chip circuitry and non-volatile memory storage. Here, we provide insight into the mechanisms that govern highly reproducible controlled resistive switching via a nanofilament by using an asymmetric metal-insulator-semiconductor structure. In-situ transmission electron microscopy is used to study in real-time the physical structure and analyze the chemical composition of the nanofilament dynamically during resistive switching. Electrical stressing using an external voltage was applied by a tungsten tip to the nanosized devices having hafnium oxide (HfO2) as the insulator layer. The formation and rupture of the nanofilaments result in up to three orders of magnitude change in the current flowing through the dielectric during the switching event. Oxygen vacancies and...

Improved NiSi salicide process using presilicide N/sub 2//sup +/ implant for MOSFETs

An improved Ni salicide process has been developed by incorporating nitrogen (N/sub 2//sup +/) implant prior to Ni deposition to widen the salicide processing temperature window. Salicided poly-Si gate and active regions of different linewidths show improved thermal stability with low sheet resistance up to a salicidation temperature of 700 and 750/spl deg/C, respectively. Nitrogen was found to be confined within the NiSi layer and reduced agglomeration of the silicide. Phase transformation to the undesirable high resistivity NiSi/sub 2/ phase was delayed, likely due to a change in the interfacial energy. The electrical results of N/sub 2//sup +/ implanted Ni-salicided PMOSFETs show higher drive current and lower junction leakage as compared to devices with no N/sub 2//sup +/ implant.

Comparative study of current–voltage characteristics of Ni and Ni(Pt)-alloy silicided p+/n diodes

A comparative study of the I–V characteristics of p+/n diodes silicided with a pure Ni and Ni(Pt) alloy has been performed. Higher saturation currents as well as abnormal reverse I–V characteristics were observed for some of the diodes which were silicided with pure Ni at 700 °C while good I–V characteristics were observed for other diodes. Our results show that the forward current in the diodes with good I–V characteristics is dominated by electron diffusion in the p+ region. For diodes with higher saturation currents, it has been concluded that both forward and reverse currents in these diodes are dominated by the current following through Schottky contacts that are formed due to inadvertent penetration of NiSi spikes through the p+ region into n region. The formation of Schottky contact was not observed in diodes silicided with a Ni(Pt) alloy, providing a clear evidence of enhanced thermal stability of Pt containing NiSi.

Modified Percolation Model for Polycrystalline High-

We modify the existing oxide breakdown (BD) percolation model in this letter to account for the presence of microstructural weakest link grain boundary (GB) defects in polycrystalline high-κ (HK) gate stacks. The different rates of the stress-induced leakage current degradation and oxide trap generation at the bulk and GB regions need to be accounted for in modeling the statistical nature of BD in HK dielectric thin films. Simulated results reveal the dominance of GB-related failures and the origin of the non-Weibull stochastics inherent in polycrystalline HK stacks. We also point to the inability of conventional percolation models with an assumed uniform defect generation to describe the failure statistics of current HK gate stacks.