Zuochang Ye

Fast floating random walk algorithm formulti-dielectric capacitance extraction with numerical characterization of Green's functions

The floating random walk (FRW) algorithm has several advantages for extracting 3D interconnect capacitance. However, for multi-layer dielectrics in VLSI technology, the efficiency of FRW algorithm would be degraded due to frequent stop of walks at dielectric interface and constraint of first-hop length especially in thin dielectrics. In this paper, we tackle these problems with the numerical characterization of Greens function for cross-interface transition probabilities and the corresponding weight value. We also present a space management technique with Octree data structure to reduce the time of each hop and parallelize the whole FRW by multi-threaded programming. Numerical results show large speedup brought by the proposed techniques for structures under the VLSI technology with thin dielectric layers.

Efficient statistical capacitance extraction of nanometer interconnects considering the on-chip line edge roughness

In this paper, efficient techniques are presented to extract the statistical interconnect capacitance due to random geometric variations, especially the line-edge roughness (LER). Based on the continuous-surface variation (CSV) model depicting wire thickness and width variations, an efficient approach is presented to calculate the capacitance sensitivity with respect to geometric variable, and further the statistical capacitance variance. The Hermite polynomial collocation (HPC) technique with variable reduction is also presented to generate the linear statistical capacitance model. Numerical experiments are carried out on structures in the 45 nm down to the 19 nm technologies. The results demonstrate the presented approaches are several orders of magnitude faster than the MC simulation with 5000 samples. The error of the sensitivity-based approach is less than 10% for the 45 nm structures, while the HPC-based technique exhibits better accuracy, even for the 19 nm structures with strong LER effect.

Co-Design of 60-GHz Wideband Front-End IC With On-Chip T/R Switch Based on Passive Macro-Modeling

Co-design of 60-GHz wideband front-end integrated circuit (IC) with on-chip transmit/receive (T/R) switch in 65-nm CMOS is presented. Passive macro-modeling (pmm) is utilized to convert S-parameter files from passive component electromagnetic simulations to state-space models in circuit netlist format that could be used in a commercial SPICE simulator for various analyses without convergence issues. The co-design of the on-chip switch and the low-noise amplifier (LNA)/power amplifier could achieve wideband matching and reduce the effects of insertion loss of the on-chip T/R switch. Combining with the gain-boosting technique in the LNA design and lumped-component-based design methodology, the implemented 60-GHz front-end IC with an on-chip T/R switch achieves 3-dB gain bandwidth (BW) of 12 GHz with a maximum gain of 17.8 dB and minimum noise figure of 5.6 dB in the receiver mode and 3-dB gain BW of 10 GHz with saturated output power of 5.6 dBm in the transmitter mode, and only consumes 1.0 mm × 1.2 mm die area (including pads).

Efficient importance sampling for high-sigma yield analysis with adaptive online surrogate modeling

Massively repeated structures such as SRAM cells usually require extremely low failure rate. This brings on a challenging issue for Monte Carlo based statistical yield analysis, as huge amount of samples have to be drawn in order to observe one single failure. Fast Monte Carlo methods, e.g. importance sampling methods, are still quite expensive as the anticipated failure rate is very low. In this paper, a new method is proposed to tackle this issue. The key idea is to improve traditional importance sampling method with an efficient online surrogate model. The proposed method improves the performance for both stages in importance sampling, i.e. finding the distorted probability density function, and the distorted sampling. Experimental results show that the proposed method is 1e2X∼1e5X faster than the standard Monte Carlo approach and achieves 5X∼22X speedup over existing state-of-the-art techniques without sacrificing estimation accuracy.

Importance Boundary Sampling for SRAM Yield Analysis With Multiple Failure Regions

SRAM cells generally require an extremely low failure rate (i.e., high yield) in the per cell basis to ensure a reasonably moderate yield for the whole chip. Existing yield analysis methods still encounter issues related to multiple failure regions resulting from high-dimensional process parameter space and/or multiple performance specifications. This paper proposes a new method that combines the advantages of existing importance sampling and boundary searching methods, and avoids issues in both. The key idea is to first find all likely failure regions and then, do importance sampling on these regions. Surrogate models are used to further accelerate the method so that SPICE-simulations can be highly reduced. Experimental results show that the proposed method is suitable for handling problems with multiple failure regions. Meanwhile, it can provide 5X ~ 20X speed-up over other existing techniques.

Statistical Analysis of Process Variations in RF/mm-Wave Circuits With On-The-Fly Passive Macro-Modeling

Process variations in passive components, e.g., inductors, transformers, baluns, and transmission lines, are increasingly degrading the performance and production yield in RF/mm-wave circuits with technology scaling. Traditional statistical analysis methods are not suitable for RF/mm-wave circuits as time-consuming EM simulation needs to be performed many times. In this paper, a statistical analysis framework is proposed for RF/mm-wave circuits considering both active and passive components. Active components are modeled in the standard way and passive components are described with a modified response surface model using a projection-based technique, which reduces the required number of EM simulation to O(N) . During the statistical analysis, the S-parameter of passive components is translated into a noise companion state-space model by passive macro-modeling to support frequency-domain, time-domain, and noise analysis. The proposed method has been justified and applied with some examples designed for a realistic 60-GHz CMOS receiver front-end. The results show that active and passive components have comparable and significant contribution to the variation of circuit performance.

Efficient 3-d capacitance extraction considering lossy substrate with multilayered green's function

An efficient algorithm for extraction of three-dimensional (3-D) capacitance on multilayered and lossy substrates is presented. The new algorithm presents a major improvement over the quasi-3-D approach used in a Greens function-based solver and takes into consideration the sidewalls of 3-D conductors. To improve the efficiency of the computation and the transformation of the Greens function, a nonuniform grid is adopted. The most computationally intensive part in the transformation of the Greens function is computed separately as technology-independent matrices Tk foremost. Once computed, Tk can be stored and used for any technology, thus the storage requirement and computational complexity are reduced from O (S/sup 2/) and O (S/sup 2/ log S/sup 2/), respectively, to just O [(log S/sub max/)/sup 2/]. Extensive tests have been performed to verify the new algorithm, and its accuracy has been established by comparing with other programs.

A Low Power Inductorless Wideband LNA With G m Enhancement and Noise Cancellation

This letter presents the design of an inductorless low power differential low-noise amplifier (LNA) in 65 nm Low Power (LP) CMOS technology for multi-standard radio applications between 100MHz and 4.3 GHz. Based on the combination of common-gate (CG) and common-source (CS) with shunt feedback (SFB) topologies, the LNA utilizes a cross-coupled push-pull structure to realize gm boosting and partial noise cancelling under low power consumption. A cascode transistor is used to alleviate the Miller effect and also constructs a current steering structure to increase the bandwidth and gain. These techniques result in a good overall performance tradeoff after sizing and biasing optimization under the power constraint. A prototype has been implemented and it exhibits a voltage gain of 21.2 dB, an NF of 2.8-4 dB over the frequency range of 100 MHz to 4.3 GHz. It consumes 2 mW from 1.2 V supply and occupies an active area of 0.05 mm2.

An Efficient SRAM Yield Analysis and Optimization Method With Adaptive Online Surrogate Modeling

SRAM cells usually require extremely low failure rate or equivalently extremely high production yield, making it impractical to perform yield analysis using Monte Carlo (MC) method as huge amount of samples are needed. Fast MC methods, e.g., importance sampling methods, are still too expensive as the anticipated failure rate is very low. In this paper, a new SRAM yield analysis method is proposed to tackle this issue. The key idea is to improve traditional importance sampling method with an efficient online surrogate model. Experimental results show that the proposed yield analysis method achieves

Pmm: A Matlab toolbox for passive macromodeling in RF/mm-wave circuit design

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