A. Bayerl

Degradation of polycrystalline HfO2-based gate dielectrics under nanoscale electrical stress

The evolution of the electrical properties of HfO2/SiO2/Si dielectric stacks under electrical stress has been investigated using atomic force microscope-based techniques. The current through the grain boundaries (GBs), which is found to be higher than thorough the grains, is correlated to a higher density of positively charged defects at the GBs. Electrical stress produces different degradation kinetics in the grains and GBs, with a much shorter time to breakdown in the latter, indicating that GBs facilitate dielectric breakdown in high-k gate stacks.

Tuning graphene morphology by substrate towards wrinkle-free devices: Experiment and simulation

Graphene grown by chemical vapor deposition can be used as the conductive channel in metal oxide semiconductor field effect transistors, metallic electrodes in capacitors, etc. However, substrate-induced corrugations and strain-related wrinkles formed on the graphene layer impoverish the properties of these devices by lowering the conductance and increasing their variability. Using the scanning electron microscopy, Auger electron spectroscopy, scanning tunneling microscopy, and atomic force microscopy, we investigated the morphology of as-grown and transferred graphene sheets on different substrates. We show that while the compressive strain (from the growth process) in the graphene sheet on flat substrates is minimized by generating wrinkles, and on rough substrates, it can be minimized by improving the graphene-substrate adhesion, leading to lower densities of wrinkles. This method paves the way to the design of wrinkle-free graphene based devices.

Graphene-Coated Atomic Force Microscope Tips for Reliable Nanoscale Electrical Characterization

Graphene single-layer films are grown by chemical vapor deposition and transferred onto commercially available conductive tips for atomic force microscopy. Graphene-coated tips are much more resistant to both high currents and frictions than commercially available, metal-varnished, conductive atomic force microscopy tips, leading to much larger lifetimes and more reliable imaging due to a lower tip-sample interaction.

Electrical and mechanical performance of graphene sheets exposed to oxidative environments

AbstractGraphene coatings have been shown to protect the underlying material from oxidation when exposed to different media. However, the passivating properties of graphene in air at room temperature, which corresponds to the operating conditions of many electronic devices, still remain unclear. In this work, we analyze the oxidation kinetics of graphene/Cu samples in air at room temperature for long periods of time (from 1 day to 113 days) using scanning electron microscopy, conductive atomic force microscopy and Auger electron microscopy, and we compare the results with those obtained for similar samples treated in H2O2. We observe that unlike the graphene sheets exposed to H2O2, in which the accumulation of oxygen at the graphene domain boundaries evolves in a very controlled and progressive way, the local oxidation of graphene in air happens in a disordered manner. In both cases the oxide hillocks formed at the graphene domain boundaries can propagate to the domains until reaching a limiting width and height. Our results demonstrate that the local oxidation of the underlying material along the domain boundaries can dramatically decrease the roughness, conductivity, mechanical resistance and frictional characteristics of the graphene sheet, which reduces the performance of the whole device.

Gate current analysis of AlGaN/GaN on silicon heterojunction transistors at the nanoscale

The gate leakage current of AlGaN/GaN (on silicon) high electron mobility transistor (HEMT) is investigated at the micro and nanoscale. The gate current dependence (25–310 °C) on the temperature is used to identify the potential conduction mechanisms, as trap assisted tunneling or field emission. The conductive atomic force microscopy investigation of the HEMT surface has revealed some correlation between the topography and the leakage current, which is analyzed in detail. The effect of introducing a thin dielectric in the gate is also discussed in the micro and the nanoscale.

Nanoscale investigation of AlGaN/GaN-on-Si high electron mobility transistors

AlGaN/GaN HEMTs are devices which are strongly influenced by surface properties such as donor states, roughness or any kind of inhomogeneity. The electron gas is only a few nanometers away from the surface and the transistor forward and reverse currents are considerably affected by any variation of surface property within the atomic scale. Consequently, we have used the technique known as conductive AFM (CAFM) to perform electrical characterization at the nanoscale. The AlGaN/GaN HEMT ohmic (drain and source) and Schottky (gate) contacts were investigated by the CAFM technique. The estimated area of these highly conductive pillars (each of them of approximately 20-50 nm radius) represents around 5% of the total contact area. Analogously, the reverse leakage of the gate Schottky contact at the nanoscale seems to correlate somehow with the topography of the narrow AlGaN barrier regions producing larger currents.

Nanoscale observations of resistive switching high and low conductivity states on TiN/HfO2/Pt structures

Abstract Resistive Switching (RS) phenomenon in Metal–Insulator–Metal (MIM) structures with polycrystalline HfO 2 layers as dielectric has been studied at the nanoscale using Conductive Atomic Force Microscope (CAFM). The CAFM measurements reveal that (i) the conductive filaments (CFs) created at very small areas are the origin of the RS phenomenon observed at device level and (ii) RS conductive filaments are primarily formed at the grain boundaries, which exhibit especially low breakdown voltage. CAFM images obtained on MIM structures at the Low and High Resistive states also show that, although the current in the Low Resistive State is mainly driven by a completely formed single CF, the cell area dependence of the conductivity in the High Resistive State could be explained by considering the presence of multiple partially formed CFs.

Nanoscale and Device Level Gate Conduction Variability of High-k Dielectrics-Based Metal-Oxide-Semiconductor Structures

The polycrystalline microstructure of the high-k dielectric of gate stacks in metal-oxide-semiconductor (MOS) devices can be a potential source of variability. In this paper, a conductive atomic force microscope (CAFM) and a Kelvin probe force microscope (KPFM) have been used to investigate how the thickness and the crystallization (after a thermal annealing) of the high-k layer affect the nanoscale morphological and electrical properties of the gate stack. The impact of such nanoscale properties on the reliability and variability of the global gate electrical characteristics of fully processed MOS devices has also been investigated.

Development of a conductive atomic force microscope with a logarithmic current-to-voltage converter for the study of metal oxide semiconductor gate dielectrics reliability

A new configuration of conductive atomic force microscope (CAFM) is presented, which is based in a conventional AFM with a logarithmic current-to-voltage (log I-V) amplifier. While a standard CAFM allows to measure a current dynamic range of typically three orders of magnitude (0.1–100pA), with the new setup it is possible to measure up to nine orders of magnitude. The extended current range allows to evaluate the reliability of gate dielectrics in a single electrical test, overcoming the limitations of standard CAFM configurations. The setup has been tested by analyzing breakdown (BD) spots induced in SiO2 and high-k layers. For current measurements, the results show that I-V characteristics and current images (measured at a constant voltage) can be easily obtained in a wide dynamic range, which can reveal new details of the BD mechanisms. In particular, the setup was used to investigate the area electrically affected by the breakdown event in SiO2 and HfO2∕SiO2 stacks.

A Conductive AFM Nanoscale Analysis of NBTI and Channel Hot-Carrier Degradation in MOSFETs

This paper addresses the impact of different electrical stresses on nanoscale electrical properties of the MOSFET gate dielectric. Using a conductive atomic force microscope (CAFM) for the first time, the gate oxide has been analyzed after bias temperature instability (BTI) and channel hot-carrier (CHC) stresses. The CAFM explicitly shows that while the degradation induced along the channel by a negative BTI stress is homogeneous, after a CHC stress different degradation levels can be distinguished, being higher close to source and drain.