Xavier Aymerich

Soft breakdown conduction in ultrathin (3-5 nm) gate dielectrics

Prior to any attempt to model a charge transport mechanism, a precise knowledge of the parameters on which the current depends is essential. In this work, the soft breakdown (SBD) failure mode of ultrathin (3-5 nm) SiO/sub 2/ layers in polysilicon-oxide-semiconductor structures is investigated. This conduction regime is characterized by a large leakage current and by multilevel current fluctuations, both at low applied voltages. In order to obtain a general picture of SBD, room-temperature current-voltage (I-V) measurements have been performed on samples with different gate areas, oxide thicknesses and substrate types. An astounding matching between some of these I-V characteristics has been found. The obtained results and the comparison with the final breakdown regime suggest that the current flow through a SBD spot is largely influenced by its atomic-scale dimensions as occurs in a point contact configuration. Experimental data are also presented which demonstrate that specific current fluctuations can be ascribed to a blocking behavior of unstable SBD conduction channels.

Resistive switching in hafnium dioxide layers: Local phenomenon at grain boundaries

Overcoming challenges associated with implementation of resistive random access memory technology for non-volatile information storage requires identifying the material characteristics responsible for resistive switching. In order to connect the switching phenomenon to the nano-scale morphological features of the dielectrics employed in memory cells, we applied the enhanced conductive atomic force microscopy technique for in situ analysis of the simultaneously collected electrical and topographical data on HfO2 stacks of various degrees of crystallinity. We demonstrate that the resistive switching is a local phenomenon associated with the formation of a conductive filament with a sufficiently small cross-section, which is determined by the maximum passing current. Switchable filament is found to be formed at the dielectric sites where the forming voltages were sufficiently small, which, in the case of the stoichiometric HfO2, is observed exclusively at the grain boundary regions representing low resistant...

Nanometer-scale analysis of current limited stresses impact on SiO/sub 2/ gate oxide reliability using C-AFM

A conductive atomic force microscope (C-AFM) has been used to analyze at a nanometer scale the impact of the current limitation on the breakdown (BD) of thin (<6 nm) SiO/sub 2/ gate oxides of metal-oxide-semiconductor (MOS) structures. The high-lateral resolution of the technique (/spl sim/10 nm) allows to get more insight in the BD phenomenology and to study, independently, the effect of the current limit on different post-BD oxide properties such as the oxide conductivity at the primary location where the event is triggered (S/sub 0/) and the size of the broken-down region (S/sub BD/). The results show that the conductivity at S/sub 0/, the total area affected by the BD and the structural damage of the oxide increase when a current limitation is not imposed during the electrical stress, leading to harder BD events. The results demonstrate that the C-AFM is a very suitable tool to perform a complete analysis of the BD phenomenology at such reduced scale.

Current limited stresses of SiO/sub 2/ gate oxides with conductive atomic force microscope

Current limitation effects on the breakdown (BD) of ultrathin SiO/sub 2/ layers have been analyzed at a nanometric scale with a conductive atomic force microscope (C-AFM). Bare oxide regions have been stressed and broken down using the tip of the C-AFM as the metal electrode of a metal-oxide-semiconductor (MOS) structure. BD induced negative charge (BINC) has been observed at the BD location, which has been related to the structural damage generated by the BD event. Moreover, BD, although triggered at one point, is electrically propagated to neighbor regions. The area affected by BD and the amount of BINC (the structural damage) depend on the breakdown hardness. In particular, it is shown that both magnitudes are smaller when the current through the structure is limited during BD transient. Based on the results, a qualitative picture of the breakdown process is presented, which accounts for the current limitation effects.

Gate Oxide Wear-Out and Breakdown Effects on the Performance of Analog and Digital Circuits

To investigate the impact of gate oxide degradation and breakdown (BD) on complimentary metal-oxide-semiconductor circuit functionality, an accurate description of the electrical characteristics of the stressed devices, which can be included in circuit simulators, is needed. In this paper, a description of the stressed device performance that considers, on the one hand, the variation of the channel current and, on the other, the increase in the gate current due to the oxide degradation and BD is presented, which is able to account for different levels of oxide damage. The parameters extracted from device experimental data have been introduced in a circuit simulator to evaluate the effect of the oxide degradation and BD on simple analog (current mirror) and digital [reset set (RS) latches] circuits. The impact of the increase in the gate leakage current and the variation of the conduction along the metal-oxide-semiconductor field-effect transistor channel due to the oxide degradation on the circuit performances has been separately analyzed.

UHV CAFM characterization of high-k dielectrics: Effect of the technique resolution on the pre- and post-breakdown electrical measurements

Abstract In this work, a Conductive Atomic Force Microscopy (CAFM) working in contact mode has been used to compare the measured electrical properties and breakdown (BD) on ultra thin high-k dielectrics, when different environmental conditions are used. In particular, the effect of the environment on the conductivity measurements, the lateral resolution in current images and the lateral propagation of the BD event will be analyzed in air, dry nitrogen (N 2 ) and Ultra High Vacuum (UHV).

Atomic force microscope topographical artifacts after the dielectric breakdown of ultrathin SiO2 films

Abstract Atomic force microscopy based techniques have been used to analyse at a nanometer scale the topographical features measured in microelectronic SiO 2 layers after their dielectric breakdown (BD). The results show that the morphological changes are not real modifications of the oxide surface, but a consequence of the electrostatic interactions between the tip and the negative charge induced in the oxide during the BD event.

Polycrystallization effects on the nanoscale electrical properties of high-k dielectrics

In this study, atomic force microscopy-related techniques have been used to investigate, at the nanoscale, how the polycrystallization of an Al2O3-based gate stack, after a thermal annealing process, affects the variability of its electrical properties. The impact of an electrical stress on the electrical conduction and the charge trapping of amorphous and polycrystalline Al2O3 layers have been also analyzed.

Degradation and breakdown of thin silicon dioxide films under dynamic electrical stress

Thin oxide MOS capacitors have been subjected to dynamic voltage stresses of different characteristics (shape, amplitude and frequency) in order to analyze the transient response and the degradation of the oxide as a function of the stress parameters. The current transients observed in dynamic voltage stresses have been interpreted in terms of the charging/discharging of interface and bulk traps. As for the oxide degradation, the experimental data has been interpreted in terms of a phenomenological model previously developed for dc stresses. According to this model, the current evolution in voltage stresses is assumed to be related to the oxide wearout. The evolution of the current during bipolar voltage stresses shows the existence of two different regimes, the degradation being much faster at low frequencies than at high frequencies. In both regimes, the frequency dependence is not significant, and the change from one regime to the other takes place at a threshold frequency which depends on the oxide field. These trends are also observed in time-to-breakdown versus frequency data, thus suggesting a strong correlation between degradation and breakdown in dynamic stresses. The experimental results are discussed in terms of microscopic degradation models.

Conductivity and Charge Trapping After Electrical Stress in Amorphous and Polycrystalline

In this paper, atomic force microscopy-based techniques have been used to study, at nanoscale, the dependence of the electrical properties of Al2O3 stacks for flash memories on the annealing temperature (TA). The electrical characterization has been combined with other techniques (for example, transmission electron microscopy) that have allowed to investigate the dependence of the stack crystallization and the Si diffusion from the substrate to the gate oxide on TA. The combination of both the analyses has allowed to explore if there is a relation between the percentage of diffused silicon and material crystallization with the conductivity and charge trapping of Al2O3 stacks.