V. Iglesias

Metal oxide resistive memory switching mechanism based on conductive filament properties

By combining electrical, physical, and transport/atomistic modeling results, this study identifies critical conductive filament (CF) features controlling TiN/HfO2/TiN resistive memory (RRAM) operations. The leakage current through the dielectric is found to be supported by the oxygen vacancies, which tend to segregate at hafnia grain boundaries. We simulate the evolution of a current path during the forming operation employing the multiphonon trap-assisted tunneling (TAT) electron transport model. The forming process is analyzed within the concept of dielectric breakdown, which exhibits much shorter characteristic times than the electroforming process conventionally employed to describe the formation of the conductive filament. The resulting conductive filament is calculated to produce a non-uniform temperature profile along its length during the reset operation, promoting preferential oxidation of the filament tip. A thin dielectric barrier resulting from the CF tip oxidation is found to control filament resistance in the high resistive state. Field-driven dielectric breakdown of this barrier during the set operation restores the filament to its initial low resistive state. These findings point to the critical importance of controlling the filament cross section during forming to achieve low power RRAM cell switching.

Metal oxide RRAM switching mechanism based on conductive filament microscopic properties

By combining electrical, physical, and transport/atomistic modeling results, this study identifies critical conductive filament features controlling TiN/HfO2/TiN resistive memory operations. The forming process is found to define the filament geometry, which in turn determines the temperature profile and, consequently, the switching characteristics. The findings point to the critical importance of controlling filament dimensions during the forming process (polarity, max current/voltage, etc.).

Correlation between the nanoscale electrical and morphological properties of crystallized hafnium oxide-based metal oxide semiconductor structures

The relationship between electrical and structural characteristics of polycrystalline HfO2 films has been investigated by conductive atomic force microscopy under ultrahigh vacuum conditions. The results demonstrate that highly conductive and breakdown (BD) sites are concentrated mainly at the grain boundaries (GBs). Higher conductivity at the GBs is found to be related to their intrinsic electrical properties, while the positions of the electrical stress-induced BD sites correlate to the local thinning of the dielectric. The results indicate that variations in the local characteristics of the high-k film caused by its crystallization may have a strong impact on the electrical characteristics of high-k dielectric stacks.

Degradation of polycrystalline HfO2-based gate dielectrics under nanoscale electrical stress

The evolution of the electrical properties of HfO2/SiO2/Si dielectric stacks under electrical stress has been investigated using atomic force microscope-based techniques. The current through the grain boundaries (GBs), which is found to be higher than thorough the grains, is correlated to a higher density of positively charged defects at the GBs. Electrical stress produces different degradation kinetics in the grains and GBs, with a much shorter time to breakdown in the latter, indicating that GBs facilitate dielectric breakdown in high-k gate stacks.

Dielectric breakdown in polycrystalline hafnium oxide gate dielectrics investigated by conductive atomic force microscopy

The relationship between the topographical and electrical properties of the polycrystalline HfO2 layer has been investigated using conductive atomic force microscopy under ultrahigh vacuum conditions. Its high lateral resolution identified the grain boundaries (GBs) as a primarily conduction path through the dielectric. Electrical stress-induced breakdown sites were also found to be located at the GBs, suggesting that the polycrystalline phase of the gate dielectric may impair reliability.

Gate current analysis of AlGaN/GaN on silicon heterojunction transistors at the nanoscale

The gate leakage current of AlGaN/GaN (on silicon) high electron mobility transistor (HEMT) is investigated at the micro and nanoscale. The gate current dependence (25–310 °C) on the temperature is used to identify the potential conduction mechanisms, as trap assisted tunneling or field emission. The conductive atomic force microscopy investigation of the HEMT surface has revealed some correlation between the topography and the leakage current, which is analyzed in detail. The effect of introducing a thin dielectric in the gate is also discussed in the micro and the nanoscale.

Nanoscale investigation of AlGaN/GaN-on-Si high electron mobility transistors

AlGaN/GaN HEMTs are devices which are strongly influenced by surface properties such as donor states, roughness or any kind of inhomogeneity. The electron gas is only a few nanometers away from the surface and the transistor forward and reverse currents are considerably affected by any variation of surface property within the atomic scale. Consequently, we have used the technique known as conductive AFM (CAFM) to perform electrical characterization at the nanoscale. The AlGaN/GaN HEMT ohmic (drain and source) and Schottky (gate) contacts were investigated by the CAFM technique. The estimated area of these highly conductive pillars (each of them of approximately 20-50 nm radius) represents around 5% of the total contact area. Analogously, the reverse leakage of the gate Schottky contact at the nanoscale seems to correlate somehow with the topography of the narrow AlGaN barrier regions producing larger currents.

Nanoscale observations of resistive switching high and low conductivity states on TiN/HfO2/Pt structures

Abstract Resistive Switching (RS) phenomenon in Metal–Insulator–Metal (MIM) structures with polycrystalline HfO 2 layers as dielectric has been studied at the nanoscale using Conductive Atomic Force Microscope (CAFM). The CAFM measurements reveal that (i) the conductive filaments (CFs) created at very small areas are the origin of the RS phenomenon observed at device level and (ii) RS conductive filaments are primarily formed at the grain boundaries, which exhibit especially low breakdown voltage. CAFM images obtained on MIM structures at the Low and High Resistive states also show that, although the current in the Low Resistive State is mainly driven by a completely formed single CF, the cell area dependence of the conductivity in the High Resistive State could be explained by considering the presence of multiple partially formed CFs.

CAFM Experimental Considerations and Measurement Methodology for In-Line Monitoring and Quantitative Analysis of III–V Materials Defects

To continue technology scaling, a new generation of high-performance devices are considered to be implemented using III-V semiconductors, which need to be grown over the conventional Si substrate. However, due to the lattice mismatch between the III-V and silicon materials, the former tend to develop significant density of structural defects [specifically, threading dislocations (TDs)], which can adversely affect device electrical characteristics. Conductive atomic force microscope (CAFM) technique is among the most promising tools for the identification and analysis of TDs in a nanoscale range although obtaining reliable quantitative data requires precise controls over the measurements conditions. In this study, CAFM technique has been applied for TDs detection and analysis in III-V films, and tool requirements and measurement methodology are discussed.

Conductance of Threading Dislocations in InGaAs/Si Stacks by Temperature-CAFM Measurements

The stacks of III-V materials, grown on the Si substrate, that are considered for the fabrication of highly scaled devices tend to develop structural defects, in particular threading dislocations (TDs), which affect device electrical properties. We demonstrate that the characteristics of the TD sites can be analyzed by using the conductive atomic force microscopy technique with nanoscale spatial resolution within a wide temperature range. In the studied InGaAs/Si stacks, electrical conductance through the TD sites was found to be governed by the Poole-Frenkel emission, while the off-TDs conductivity is dominated by the thermionic emission process.