A. Carr

Tungsten and cobalt metallization: A material study for MOL local interconnects

Middle-of-the-line (MOL) interconnect and contact resistances represent significant impacts to high-end IC performance at ≤ 10 nm nodes. CVD W-based metallization has been used for all nodes since the inception of damascene. However, it is now being severely challenged due to limited scaling of the traditional PVD Ti/CVD TiN barrier and ALD nucleation layers. This study reports the use of alternate barriers, along with metal-to-metal contact interface cleans, to reduce contact resistance for W-based MOL metallization. As well, we report the first use of Co metal for MOL contacts and local interconnects, with successful integration below a Cu BEOL dual damascene V0/M1 module. Metal line resistances are compared among the various options, and the challenges with each option are highlighted.

Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET

In this paper, for the first time we demonstrate that horizontally stacked gate-all-around (GAA) Nanosheet structure is a good candidate for the replacement of FinFET at the 5nm technology node and beyond. It offers increased Weff per active footprint and better performance compared to FinFET, and with a less complex patterning strategy, leveraging EUV lithography. Good electrostatics are reported at Lg=12nm and aggressive 44/48nm CPP (Contacted Poly Pitch) ground rules. We demonstrate work function metal (WFM) replacement and multiple threshold voltages, compatible with aggressive sheet to sheet spacing for wide stacked sheets. Stiction of sheets in long-channel devices is eliminated. Dielectric isolation is shown on standard bulk substrate for sub-sheet leakage control. Wrap-around contact (WAC) is evaluated for extrinsic resistance reduction.

Defect and grain boundary scattering in tungsten: A combined theoretical and experimental study

Several major electron scattering mechanisms in tungsten (W) are evaluated using a combination of first-principles density functional theory, a Non-Equilibrium Greens Function formalism, and thin film Kelvin 4-point sheet resistance measurements. The impact of grain boundary scattering is found to be roughly an order of magnitude larger than the impact of defect scattering. Ab initio simulations predict average grain boundary reflection coefficients for a number of twin grain boundaries to lie in the range r = 0.47 to r = 0.62, while experimental data can be fit to the empirical Mayadas-Schatzkes model with a comparable but slightly larger value of r = 0.69. The experimental and simulation data for grain boundary resistivity as a function of grain size show excellent agreement. These results provide crucial insights for understanding the impact of scaling of W-based contacts between active devices and back-end-of-line interconnects in next-generation semiconductor technology.

Highly-selective superconformai CVD Ti silicide process enabling area-enhanced contacts for next-generation CMOS architectures

We investigate a novel Ti Chemical Vapor Deposition (CVD Ti) technique for source/drain and trench contact silicidation. This work is a first demonstration of a highly selective, superconformal Ti process that exhibits a low p-type CVD Ti/SiGe:B contact resistivity (pc) down to 2.1×10⁻⁹ Ω.cm² (a 40% reduction vs. PVD Ti), matching the lowest published values [1-5]. A competitive n-type CVD Ti/Si:P with a ρ<inf>c</inf> at 2.6×10⁻⁹ Ω.cm² is measured. We demonstrate up to 90% superconformality for this process, with a tunnel silicidation at lengths up to 500nm, showing an exceptional selectivity to oxide. This process is an enabler for the next generation of area-enhanced contact CMOS architectures.

Dual beam laser annealing for contact resistance reduction and its impact on VLSI integrated circuit variability

Introduction of a dual beam (DB) millisecond (mSec) or nanosecond (nSec laser annealing in contact module results in a drastic reduction of contact resistivity. Dependence of this benefit on laser annealing parameters is detailed. The annealing power/temperature condition needed for initiating solid or liquid phase epitaxy (SPE, LPE defines a lower process boundary, while impact of laser annealing on transistor parameters, such as Vt and gate stack, defines an upper process boundary and translates to with-in-die (WID Vt variation. Combining DB laser annealing technique with process-friendly layouts enables contact resistance benefit without degrading product level variability.

Formation and microstructure of thin Ti silicide films for advanced technologies

We report on the solid-state reaction of thin PVD Ti films with in-situ doped Si & SiGe alloys using a combination of in-situ x-ray diffraction, sheet resistance, laser light scattering measurements and ex-situ x-ray pole figure analysis. Thin Ti films or thin bilayer films (Ni/Ti or NiPt/Ti) are found to be much more aligned with the underlying substrates. Millisecond laser anneals also lead to the introduction of strong in-plane texture.

Interface preservation during Ge-rich source/drain contact formation

Contact engineering of Ge-rich source/drain is of critical importance for the development of advanced nano-scale CMOS technology nodes. Germanosilicide or Germanide contacts with low Schottky barrier height are highly desirable to achieve low contact resistance for a Ge-rich source/drain. However, practical integration of Ge-rich SiGe into devices is complicated by its unique physical and chemical properties as compared to Si-rich epitaxial SiGe. We have observed significant erosion along the SiGe interface with its dielectric cap layer. The N2-H2 remote plasma resist strip process has been shown to trigger this erosion when GeO2 exists together with SiO2 at the interface. The integrity of Ge-rich SiGe contact interface can be preserved by replacing the N2-H2 remote plasma resist strip with an O2-based photoresist ash process. Cross-sectional STEM and EDX elemental analysis have confirmed Germanide and Germanosilicide formation at the Ge-rich SiGe contact interface.