Zuoguang Liu

A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels

We present a 7nm technology with the tightest contacted poly pitch (CPP) of 44/48nm and metallization pitch of 36nm ever reported in FinFET technology. To overcome optical lithography limits, Extreme Ultraviolet Lithography (EUV) has been introduced for multiple critical levels for the first time. Dual strained channels have been also implemented to enhance mobility for high performance applications.

A novel ALD SiBCN low-k spacer for parasitic capacitance reduction in FinFETs

FinFET has become the mainstream logic device architecture in recent technology nodes due to its superior electrostatic and leakage control [1,2,3,4]. However, parasitic capacitance has been a key performance detractor in 3D FinFETs. In this work, a novel low temperature ALD-based SiBCN material has been identified, with an optimized spacer RIE process developed to preserve the low-k value and provide compatibility with the down-stream processes. The material has been integrated into a manufacturable 14nm replacement-metal-gate (RMG) FinFET baseline with a demonstrated ~8% performance improvement in the RO delay with reliability meeting the technology requirement [4]. A guideline for spacer design consideration for 10nm node and beyond is also provided based on the comprehensive material properties and reliability evaluations.

Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET

In this paper, for the first time we demonstrate that horizontally stacked gate-all-around (GAA) Nanosheet structure is a good candidate for the replacement of FinFET at the 5nm technology node and beyond. It offers increased Weff per active footprint and better performance compared to FinFET, and with a less complex patterning strategy, leveraging EUV lithography. Good electrostatics are reported at Lg=12nm and aggressive 44/48nm CPP (Contacted Poly Pitch) ground rules. We demonstrate work function metal (WFM) replacement and multiple threshold voltages, compatible with aggressive sheet to sheet spacing for wide stacked sheets. Stiction of sheets in long-channel devices is eliminated. Dielectric isolation is shown on standard bulk substrate for sub-sheet leakage control. Wrap-around contact (WAC) is evaluated for extrinsic resistance reduction.

Ti and NiPt/Ti liner silicide contacts for advanced technologies

We discuss the transition to Ti based silicides for source-drain (SD) contacts for 3D FinFET devices starting from the 14nm node & beyond. Reductions in n-FET & p-FET contact resistances are reported with the optimization of metallization process & dopant concentrations. The optimization of SiGe epitaxy and addition of a thin interfacial NiPt(10%) are found to significantly improve p-FET contact performance.

Sub-

We report record low 8.4 × 10^-10 Ω-cm² n-type S/D contact resistivity with laser-induced solid/liquid phase epitaxy of Si:P inside nano-scale contact trenches. Significant reduction of device resistance and resultant great gain of drain current has been demonstrated in scaled n-FinFETs with a contact length of 20 nm.

10^{-9}~\Omega

We achieved mid-10⁻¹⁰ Ω-cm² n-type S/D contact resistivity (npc) and 1.9×10⁻⁹ Ω-cm² p-type S/D contact resistivity (ppc) by employing laser-induced liquid or solid phase epitaxy (LPE/SPE) of Si:P and Ge:Group-III-Metal metastable alloys inside nano-scale contact trenches. The Ge: Group-III-Metal alloy allows for a metal-Ge Fermi level pinning effect to lower Schottky barrier height (SBH) while reducing both bulk and unipolar heterojunction resistances. Correspondingly, large Ron reduction and Id gain have been realized in scaled n- and p-FinFETs with the contact length of less than 20nm.

-cm2 n-Type Contact Resistivity for FinFET Technology

For the first time, we report integration of air spacers with FinFET technology at 10nm node dimensions. The benefit of parasitic capacitance reduction by air spacers has been successfully demonstrated both at transistor level (15–25% reduction in overlap capacitance (COT)) and at ring oscillator level (10–15% reduction in effective capacitance (Cf)). Key process challenges and device implications of integrating air spacers in FinFET are identified. We propose a partial air spacer scheme, in which air spacers are formed only above fin top and sandwiched by two dielectric liners, as a viable option to adopt air spacers in FinFET technology with minimal risks to yield and reliability.

FinFET performance with Si:P and Ge:Group-III-Metal metastable contact trench alloys

Low Ge content SiGe-based CMOS FinFET is one of the promising technologies [1-2] offering solutions for both high performance and low power applications. In this paper, we established a competitive SiGe-based CMOS FinFET baseline and examined various elements for high performance offering. The performance elements in gate stack, channel doping, contact resistance, and junction have been explored to provide a cumulative 20% / 25% (n/pFET) performance enhancement. These elements provide a viable path towards performance enhancement for future technology nodes.

Air spacer for 10nm FinFET CMOS and beyond

A fast two-point measurement methodology, applicable to nano-scale devices, is introduced to separate electron trapping (Not, e) from interface state contributions (Nit) in hot carrier (HC) induced ΔVt in n-type RMG SOI FinFETs. It is shown that Not, e component is comparable to or dominates over Nit for high-Vg (≥ Vd) hot carrier stress (HCS). The time power-law exponent for HC induced Not, e is larger than 0.2, indicating the observed Not, e is partly due to injection of hot carriers instead of purely parasitic PBTI effect caused by the cold carriers.

Technology viable DC performance elements for Si/SiGe channel CMOS FinFTT

Introduction of a dual beam (DB) millisecond (mSec) or nanosecond (nSec laser annealing in contact module results in a drastic reduction of contact resistivity. Dependence of this benefit on laser annealing parameters is detailed. The annealing power/temperature condition needed for initiating solid or liquid phase epitaxy (SPE, LPE defines a lower process boundary, while impact of laser annealing on transistor parameters, such as Vt and gate stack, defines an upper process boundary and translates to with-in-die (WID Vt variation. Combining DB laser annealing technique with process-friendly layouts enables contact resistance benefit without degrading product level variability.