J. Demarest

A 0.063 µm 2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch

We demonstrate the smallest FinFET SRAM cell size of 0.063 µm2 reported to date using optical lithography. The cell is fabricated with contacted gate pitch (CPP) scaled to 80 nm and fin pitch scaled to 40 nm for the first time using a state-of-the-art 300 mm tool set. A unique patterning scheme featuring double-expose, double-etch (DE2) sidewall image transfer (SIT) process is used for fin formation. This scheme also forms differential fin pitch in the SRAM cells, where epitaxial films are used to merge only the tight pitch devices. The epitaxial films are also used for conformal doping of the devices, which reduces the external resistance significantly. Other features include gate-first metal gate stacks and transistors with 25 nm gate lengths with excellent short channel control.

22 nm technology compatible fully functional 0.1 μm 2 6T-SRAM cell

We demonstrate 22 nm node technology compatible, fully functional 0.1 mum2 6T-SRAM cell using high-NA immersion lithography and state-of-the-art 300 mm tooling. The cell exhibits a static noise margin (SNM) of 220 mV at Vdd=0.9 V. We also present a 0.09 mum2 cell with SNM of 160 mV at Vdd=0.9 V demonstrating the scalability of the design with the same layout. This is the worlds smallest 6T-SRAM cell. Key enablers include band edge high-kappa metal gate stacks, transistors with 25 nm gate lengths, thin spacers, novel co-implants, advanced activation techniques, extremely thin silicide, and damascene copper contacts.

UTBB FDSOI transistors with dual STI for a multi-V t strategy at 20nm node and below

We introduce an innovative dual-depth shallow trench isolation (dual STI) scheme for Ultra Thin Body and BOX (UTBB) FDSOI architecture. Since in the dual STI configuration wells are isolated from one another by the deepest trenches, this architecture enables a full use of the back bias while staying compatible with both standard bulk design and conventional SOI substrates. We demonstrate in 20nm ground rules that we are able to tune Vt by more than 400mV, that transistor performance can be boosted by up to 30% and that Ioff can be controlled over 3 decades by allowing more than VDD/2 to be applied on the back gate.

The Effect of Metal Area and Line Spacing on TDDB Characteristics of 45nm Low-k SiCOH Dielectrics

Low-k time-dependent dielectric breakdown (TDDB) is rapidly becoming one of the most important reliability issues in Cu/low-k technology development and qualification. Although considerable progress has been made in recent years in addressing the electric field dependence of low-k time-to-breakdown (tBD), there has been very little comprehensive work done on the effect of metal area and line spacing on low-k TDDB. The lifetime of a product chip is typically obtained by extrapolating TDDB data from small test structures to large chip areas, and the low-k TDDB line spacing scaling rule normally should be considered for the definition of operating voltages for various technologies to assure long-term reliability. Therefore, both area scaling and line spacing scaling relations are of great importance, in order to have a robust technology qualification. In this study, a thorough investigation into the 45 nm low-k SiCOH TDDB was conducted in order to understand the breakdown failure statistics, to model the area dependence, and to explore the line spacing scaling. With the help of experimental results and computational simulations, the effect of line-to-line spacing on low-k TDDB was clearly identified and a methodology for accurate determination of Weibull shape factor is proposed.

Chip-to-package interaction for a 90 nm Cu / PECVD low-k technology

A summary of chip-to-package interaction (CPI) evaluations for a 90 nm PECVD low k technology will be discussed. This review will cover a 90 nm technology that uses Cu dual damascene interconnections with a SiCOH (K /spl sim/ 3.0) CVD BEOL insulator stack across multiple wirebond package types and flipchip C4 ceramic and organic packages. It will be shown that with the use of IBMs internally engineered SiCOH BEOL insulator, CPI is not an issue with this technology node.

The effect of a threshold failure time and bimodal behavior on the electromigration lifetime of copper interconnects

Electromigration results are described for a Dual Damascene structure with copper metallization and a low-k dielectric material. The failure times follow a bimodal lognormal behavior with early and late failures. Moreover, there is evidence of a threshold failure time such that each failure mode is represented by a 3-parameter lognormal distribution. It is found that the threshold failure time scales differently with current density from the median time to failure, which can be explained by considering two components of the electromigration lifetime: one controlled by void nucleation and the other controlled by void growth.

A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels

We present a 7nm technology with the tightest contacted poly pitch (CPP) of 44/48nm and metallization pitch of 36nm ever reported in FinFET technology. To overcome optical lithography limits, Extreme Ultraviolet Lithography (EUV) has been introduced for multiple critical levels for the first time. Dual strained channels have been also implemented to enhance mobility for high performance applications.

Thermal cycle reliability of stacked via structures with copper metallization and an organic low-k dielectric

The reliability of a stacked via chain stressed under various thermal cycle conditions is described. The chain consists of Cu Dual Damascene metallization with SiLK (trademark of Dow Chemical) as the organic low-k dielectric. Failure analysis indicates that cracks form in the Cu vias during thermal cycle stress. Due to the presence of two failure modes, the thermal cycle statistical behavior is described by a bimodal lognormal failure distribution. The thermal cycle lifetime exhibits a strong dependence on the temperature range and a rather weak dependence, on the maximum temperature in the cycle. Evidence of a threshold temperature range below which thermal cycle fails should not occur as well as a correlation between the test structure yield and reliability are also reported.

Electromigration Challenges for Nanoscale Cu Wiring

Electromigration data and a theoretical model have shown that Cu lifetime in on‐chip Damascene interconnect structures has dropped for every new interconnect generation, even when tested at the same current density. In addition, a mixture of bamboo and polycrystalline grain structures instead of a bamboo‐like structure observed for <90 nm wide lines (65 nm technology node) resulted in further lifetime degradation by the addition of grain boundary diffusion. The techniques for improving EM lifetime either by modifying the interconnect structure by adding dummy vias on top of a Cu line, a Ru cap on the Cu top surface, or the formation of a thin CuSiN layer at the Cu/dielectric interface were investigated. The upper dummy vias, the Ru cap or CuSiN layer on the top surface of the Cu lines interrupted the Cu mass flow along the top surface interface which can improve lifetimes. The upper level dummy via structure was a powerful tool for helping to understand the Cu microstructure and to distinguish fast diffus...

Prototype of multi-stacked memory wafers using low-temperature oxide bonding and ultra-fine-dimension copper through-silicon via interconnects

Reported for the first time is proof-of-concept multi-stacking of memory wafers based on low-temperature oxide wafer bonding using novel design and integration of two types of ultra-fine-dimension copper TSV interconnects. The combined via-middle (intra-via) and via-last (inter-via) strategy allows for the greatest degree of interconnectivity with the tightest allowable pitches and permits a highly integrated interconnect system across the stack. In combination with the successful metallization of the ultra-fine-dimension TSVs, the present work has shown the viability to extend the perceived TSV technology beyond the ITRS roadmap.