Ralf Ludewig

Hinoc: A Hierarchical Generic Approach for on-Chip Communication, Testing and Debugging of SoCs

This paper presents a new generic system architecture and design methodology for the design, debugging and testing of complex systems-on-chip (SoC). Starting from a hierarchical generic system architecture, platforms for dedicated application scenarios will be customized. In order to be able to handle very complex submicron designs, the system is based on a globally asynchronous and locally synchronous (GALS) concept. The problem of the increasing functionality versus outer access capabilities ratio is faced by novel embedded and combined debugging and test structures. The integration of debugging possibilities is essential for an efficient co-design of SoC integrated hardware and software, especially for systems with integrated reconfigurable hardware parts.

Prototyping of a high performance generic Viterbi decoder

For its proven efficiency, the Viterbi algorithm is widely used for decoding convolutionally encoded messages. In this work, a high performance generic soft input hard output Viterbi decoder is presented and prototyped on an FPGA board. The presented Viterbi decoder is intended to be used in a complete wireless LAN transceiver prototype. The genericity of the design facilitates not only the prototyping of Viterbi decoders with different specifications, but moreover it facilitates the exploration the performance of different implementations in order to obtain the most suitable solution for a particular communication system.

Power estimation based on transition activity analysis with an architecture precise rapid prototyping system

In this paper a technique is proposed to gather statistical data concerning transition activity of the interface signals in a complex application. By using an architecture precise rapid prototyping system, the signals can be analyzed over a long period of time and therefore a realistic estimation of the signal activity characteristics can be obtained. This information can be used for estimating the power consumption in the final system as well as for a later refinement of the communication structures and single processing blocks. Because of the huge amount of data that would be generated by a real time monitoring, a statistical compression module was implemented. This module allows the trade off between hardware efficiency and accuracy in order to offer a flexible use in prototyping systems. The proposed approach has been validated in a baseband implementation of a simplified OFDM transmitter.

IP Generation for an FPGA-Based Audio DAC Sigma-Delta Converter

In this paper we describe a parameterizable FPGA-based implementation of a sigma-delta converter used in a 96kHz audio DAC. From specifications of the converter’s input bitwidth and data sampling frequency, VHDL generic parameters are used to automatically generate the required design. The resulting implementation is optimized to use the minimum internal wordlength and number of stages. We prototyped the converter on an FPGA board for verification purposes and the results are presented.

Rapid prototyping of an integrated testing and debugging unit

Due to the increasing complexity of electronic systems the controllability and observability of advanced on-chip systems are getting more and more important. The functional density which is measured as the amount of functionality related to port width for outer access is permanently growing. Therefore tasks like manufacturing tests and functional debugging are becoming more difficult. In this work we present a synthesizable model for an integrated test and debugging unit which implements a build-in self test (BIST) and an advanced debugging unit. In the debugging unit the scan-chain from testing is reused to get access to internal registers. The whole unit is designed as a wrapper to system-on-chip (SoC) cores. To assess the usability of this approach the wrapper together with a processor core is prototyped and the functionality of the testing and debugging unit is demonstrated.

Emulation of analog components for the rapid prototyping of wireless baseband systems

The increasing complexity of modern wireless baseband systems demands the use of rapid prototyping methodologies to provide an early estimation of system functionality and performance. In order to achieve an efficient hardware emulation, the complete system including the analog part should be prototyped. In this work we present synthesizable descriptions of a communication channel module and a sigma delta modulator, suitable for fundamental emulation of wireless baseband environments. By avoiding time-intensive hardware/software cosimulation, a great speedup of the system verification can be attained. In order to assist the designer and speed up the design process we also created an environment for automatically customizing the modules according to a specific scenario.

Evaluation and Run-Time Optimization of On-chip Communication Structures in Reconfigurable Architectures

With technology improvements, the main bottleneck in terms of performance, power consumption, and design reuse in single chip systems is proving to be generated by the on-chip communication architecture. Benefiting from the non-uniformity of the workload in various signal processing applications, several dynamic power management policies can be envisaged. Nevertheless, the integration of on-line power, performance and information-flow management strategies based on traffic monitoring in (dynamically) reconfigurable templates has yet to be explicitly tackled. The main objective of this work is to define the concept of run-time functional optimization of application specific standard products, and show the importance of integrating such techniques in reconfigurable platforms and especially their communication architectures.

Hardware-Assisted Signal Activity Analysis for Power Estimation in Rapid Prototyped Systems

In this paper, a technique is proposed to gather statistical data concerning the activity of the internal signals in a complex application. By using an architecture precise rapid prototyping system, the signals can be analyzed over a long period of time and therefore, a realistic estimation of the signal characteristics is obtained. This information can be used for estimating the power consumption in the final system as well as for a later refinement of the communication structures and processing blocks. In order to account for deep submicron effects, not only transition activity but also inter-wire correlations are considered. Because of the huge amount of data that would be generated by a real-time monitoring, a statistical hardware compression module was implemented for embedding it into prototyped designs. It allows the trade off between hardware efficiency and estimation accuracy, in order to offer a flexible usage of the prototyping resources. The proposed approach has been validated in a baseband implementation and prototype of a simplified OFDM transmitter.

On the numerical accuracy of CORDIC-based frequency offset compensation in burst oriented OFDM systems

CORDIC (COordinate Rotation DIgital Computer)-based VLSI architectures are very interesting for the design of frequency offset estimation and correction circuits for OFDM burst oriented systems because of the simplicity of their hardware implementation. This paper evaluates the lower realizable bound on the accuracy of fixed-point CORDIC-based frequency offset estimation and correction schemes. The proposed evaluation relies on the Cramer-Rao lower bound (CRLB) and the upper bound of the error introduced by the CORDIC algorithm. Simulations results related to the application of this evaluation scheme to a HiperLAN/2 simulation model are presented.