A.J.M. van Tuijl

A 1.35 GS/s, 10 b, 175 mW Time-Interleaved AD Converter in 0.13 µm CMOS

A time-interleaved ADC is presented with 16 channels, each consisting of a track-and-hold (T&H) and two successive approximation (SA) ADCs in a pipeline configuration to combine a high sample rate with good power efficiency. The single-sided overrange architecture achieves a 25% higher power efficiency of the SA-ADC compared with the conventional overrange architecture, and look-ahead logic is used to minimize logic delay in the SA-ADC. For the T&H, three techniques are presented enabling a high bandwidth and linearity and good timing alignment. Single channel performance of the ADC is 6.9 ENOB at an input frequency of 4 GHz. Multichannel performance is 7.7 ENOB at 1.35 GS/s with an ERBW of 1 GHz. The FoM of the complete ADC including T&H is 0.6 pJ per conversion step. An improved version is presented as well and achieves an SNDR of 8.6 ENOB for low sample rates, and, with increased supply voltage, it reaches a sample rate of 1.8 GS/s with 7.9 ENOB at low input frequencies and an ERBW of 1 GHz. At fin = 3.6 GHz, the SNDR is still 6.5 ENOB, and total timing error including jitter is 0.4 ps rms.

Low-Power, High-Speed Transceivers for Network-on-Chip Communication

Networks on chips (NoCs) are becoming popular as they provide a solution for the interconnection problems on large integrated circuits (ICs). But even in a NoC, link-power can become unacceptably high and data rates are limited when conventional data transceivers are used. In this paper, we present a low-power, high-speed source-synchronous link transceiver which enables a factor 3.3 reduction in link power together with an 80% increase in data-rate. A low-swing capacitive pre-emphasis transmitter in combination with a double-tail sense-amplifier enable speeds in excess of 9 Gb/s over a 2 mm twisted differential interconnect, while consuming only 130 fJ/transition without the need for an additional supply. Multiple transceivers can be connected back-to-back to create a source-synchronous transceiver-chain with a wave-pipelined clock, operating with 6sigma offset reliability at 5 Gb/s.

A 90μW 12MHz Relaxation Oscillator with a -162dB FOM

Both ring oscillators and relaxation oscillators are subsets of RC oscillators featuring large tuning ranges and small areas. Such relaxation oscillators have two advantages with respect to ring oscillators: 1) they have a constant frequency tuning gain; and 2) their phase can be read out continuously due to their triangular (or sawtooth) waveform. A major disadvantage of practical relaxation oscillators is their poor phase-noise compared to ring oscillators.

A coupled sawtooth oscillator combining low jitter and high control linearity

A new type of current controlled oscillator (CCO) is presented that combines excelllent control linearity with low timing jitter. The problem of overshoot in traditional relaxation oscillators is solved by using an alternative for the Schmitt-trigger. Circuits realised in a 0.8µm CMOS process show a HD2 OSC =1.5 MHz for a supply current of 360µA.

A 16-bit D/A interface with sinc approximated semidigital reconstruction filter and reduced number of coefficients

Due to components nonidealities, the analog reconstruction is the most difficult analog building block in a D/A converter. The paper presents a 16-bit D/A interface with a current driven semidigital filter and reduced number of coefficients. To optimise the number of coefficients an iterative method based on Sinc approximation has been used. With only 25 coefficients we get more than 50dB stopband rejection of noise. A differential solution is proposed to reduce the digital crosstalk and to increase the output swing. The D/A interface has been realised on chip in a 0.8µm CMOS 5V technology. S/N+THD measurements are provided.