Anne-Johan Annema

Analog circuits in ultra-deep-submicron CMOS

Modern and future ultra-deep-submicron (UDSM) technologies introduce several new problems in analog design. Nonlinear output conductance in combination with reduced voltage gain pose limits in linearity of (feedback) circuits. Gate-leakage mismatch exceeds conventional matching tolerances. Increasing area does not improve matching any more, except if higher power consumption is accepted or if active cancellation techniques are used. Another issue is the drop in supply voltages. Operating critical parts at higher supply voltages by exploiting combinations of thin- and thick-oxide transistors can solve this problem. Composite transistors are presented to solve this problem in a practical way. Practical rules of thumb based on measurements are derived for the above phenomena.

A 3-Gb/s optical detector in standard CMOS for 850-nm optical communication

This paper presents a monolithic optical detector, consisting of an integrated photodiode and a preamplifier in a standard 0.18-/spl mu/m CMOS technology. A data rate of 3 Gb/s at BER <10/sup -11/ was achieved for /spl lambda/=850 nm with 25-/spl mu/W peak-peak optical power. This data rate is more than four times than that of current state-of-the-art optical detectors in standard CMOS reported so far. High-speed operation is achieved without reducing circuit responsivity by using an inherently robust analog equalizer that compensates (in gain and phase) for the photodiode roll-off over more than three decades. The presented solution is applicable to various photodiode structures, wavelengths, and CMOS generations.

Analytical Design Equations for Class-E Power Amplifiers with Finite DC-Feed Inductance and Switch On-Resistance

This paper presents the analytical solution in time domain for the ideal single-ended class-E power amplifier (PA). Based on the analytical solution a coherent noniterative procedure for choosing the circuit parameters is presented for class-E PAs with arbitrary duty-cycle and finite dc-feed inductance (e.g., continuously ranging from class-E with small finite drain inductance to class-E with RF choke). The obtained analysis results link all known class-E PA design equations as well as presenting new design equations. The result of the analysis gives more degrees of freedom to designers in their design and optimization by further expanding the design space of class-E PA.

An Interleaved Full Nyquist High-Speed DAC Technique

A 9 bit 11 GS/s DAC is presented that achieves an SFDR of more than 50 dB across Nyquist and IM3 below -50 dBc across Nyquist. The DAC uses a two-times interleaved architecture to suppress spurs that typically limit DAC performance. Despite requiring two current-steering DACs for the interleaved architecture, the relative low demands on performance of these sub-DACs imply that they can be implemented in an area and power efficient way. Together with a quad-switching architecture to decrease demands on the power supply and bias generation and employing the multiplexer switches in triode, the total core area is only 0.04 mm 2 while consuming 110 mW from a single 1.0 V supply.

Physical and electrical bandwidths of integrated photodiodes in standard CMOS technology

The influence of different geometries (layouts) and structures of high-speed photodiodes in fully standard 0.18 /spl mu/m CMOS technology on their intrinsic (physical) and electrical bandwidths is analyzed. Three photodiode structures are studied: nwell/p-substrate, p+/nwell/p-substrate and p+/nwell. The photodiode bandwidths are compared for /spl lambda/=650 nm wavelength which is used in todays DVD optical pick-ups. Slow substrate current component limits the intrinsic bandwidth of nwell/p-substrate and p+/nwell/p-substrate photodiodes to 70 MHz and 100 MHz, respectively. The electrical bandwidth of these diodes in combination with typical transimpedance amplifiers, will be larger than the calculated intrinsic bandwidths. Thus, the parasitic diode capacitance has almost no influence on the total bandwidth of both photodiodes. By using only a p+/nwell photodiode (not connecting a substrate), the intrinsic diode bandwidth is 1 GHz. However, the electrical bandwidth limitation of this diode due to its parasitic capacitance is important and can limit the total diode bandwidth which is by approximation the lower of the physical and the electrical bandwidth. The calculated responsivity of p+/nwell photodiode is 10 dB lower than in other two defined diodes structures, requiring higher sensitivity of the subsequent electronic circuitry.

Noise and Nonlinearity Modeling of Active Mixers for Fast and Accurate Estimation

This paper presents a model of active mixers for a fast and accurate estimation of noise and nonlinearity. Based on closed-form expressions, this model estimates the noise figure, IIP3, and IIP2 of the time-varying mixer by a limited number of time-invariant circuit calculations. The model shows that the decreasing transistor output resistance, together with the low supply voltage in deep-submicrometer technologies, significantly contributes to the flicker-noise leakage. Design insights for low flicker noise are then presented. The model also shows that the slope of the LO signal has a significant effect on IIP2, while it has a little effect on IIP3. A new IP2 calibration technique using slope tuning is presented.

A Flicker Noise/IM3 Cancellation Technique for Active Mixer Using Negative Impedance

This paper presents an approach to simultaneously cancel flicker noise and IM3 in Gilbert-type mixers, utilizing negative impedances. For proof of concept, two prototype double-balanced mixers in 0.16- μm CMOS are fabricated. The first demonstration mixer chip was optimized for full IM3 cancellation and partial flicker noise cancellation; this chip achieves 9-dB flicker noise suppression, improvements of 10 dB for IIP3, 5 dB for conversion gain, and 1 dB for input P1 dB while the thermal noise increased by 0.1 dB. The negative impedance increases the power consumption for the mixer by 16% and increases the die area by 8% (46 × 28 μm 2). A second demonstration mixer chip aims at full flicker noise cancellation and partial IM3 cancellation, while operating on a low supply voltage (0.67 × VDD); in this chip, the negative impedance increases the power consumption by 7.3% and increases the die area by 7% (50 × 20 μm 2). For one chip sample, measurements show >10-dB flicker noise suppression within ±200% variation of the negative impedance bias current; for ten randomly selected chip samples, >11-dB flicker noise suppression is measured.

RF Circuit Linearity Optimization Using a General Weak Nonlinearity Model

This paper focuses on optimizing the linearity in known RF circuits, by exploring the circuit design space that is usually available in todays deep submicron CMOS technologies. Instead of using brute force numerical optimizers we apply a generalized weak nonlinearity model that only involves AC transfer functions to derive simple equations for obtaining design insights. The generalized weak nonlinearity model is applied to three known RF circuits: a cascode common source amplifier, a common gate LNA and a CMOS attenuator. It is shown that in deep submicron CMOS technologies the cascode transistor in both the common source amplifier and in the common gate amplifier significantly contributes IM3 distortion. Some design insights are presented for reducing the cascode transistor related distortion, among which moderate inversion biasing that improves IIP3 by 10 dB up to 5 GHz in a 90 nm CMOS process. For the attenuator, a wideband IM3 cancellation technique is introduced and demonstrated using simulations.

A 0.0025mm 2 bandgap voltage reference for 1.1V supply in standard 0.16μm CMOS

Todays ICs usually employ one bandgap voltage reference (BGVR) circuit to generate a well defined voltage that is reused at many places in that IC. The classical BGVR generates a reference voltage that is slightly larger than the material bandgap: a little above 1200mV in silicon. For deep-sub-micron technologies the supply voltage is about the same as the material bandgap which prevents using the classical bandgap structure. As a solution a number of BGVR topologies that create a sub-1V are invented; most of them are based on the structure introduced by Banba [1], some are using resistive voltage division [2] or voltage averaging [3]. For low-power operation high-ohmic resistors (occupying a large area!) must be used in all these techniques, leading to an immediate trade-off between power consumption and chip-area. This trade-off prevents the local generation of reference voltages where they are required: either the power penalty or the area penalty would be too significant. Alternative topologies that do not require high-ohmic resistors typically are not-BGVR-based circuits relying on threshold voltages and hence require trimming to achieve low spread.

An audio FIR-DAC in a BCD process for high power class-D amplifiers

A 322 coefficient semi-digital FIR-DAC using a 1-bit PWM input signal was designed and implemented in a high voltage, audio power bipolar CMOS DMOS (BCD) process. This facilitates digital input signals for an analog class-D amplifier in BCD. The FIR-DAC performance depends on the ISI-resistant nature of this PWM-signal. An impulse response with only positive coefficients was chosen, because of its resistance to deadzone and mismatch. With a DAC current of 0.5 mA, the dynamic range is 111 dB (A-weighted), with SINAD = 103 dB (A-weighted). The current consumption is 1mA for the analog part and 4.8 mA for the digital part. The power consumption is 29 mW at V/sub dd/ = 5 V and the chip area is 2 mm/sup 2/ including the reference diode that can be shared by more channels.