A.K.M. Mahfuzul Islam

Inhomogeneous Ring Oscillator for Within-Die Variability and RTN Characterization

This paper discusses the concept of an inhomogeneous structure for a ring oscillator (RO) to enhance the delay effect of a particular inverter stage. The frequency of the proposed inhomogeneous structure becomes a strong function of the inhomogeneous stage; thus, the variability becomes directly visible. With careful design of the inhomogeneous stage, the RO frequency can be made sensitive to a small set of transistors for characterizing transistor-by-transistor variability. Performance sensitivities of the transistors are enhanced more than 100 times that of other transistors in the RO. The proposed ROs are embedded into a 65-nm RO-array test structure, and it is verified that these ROs are highly sensitive to within-die local variability and random telegraph noise (RTN). The within-die local variability is then successfully decomposed into threshold voltage and gate length variations. Several characteristics of RTN have been successfully extracted with the proposed structure. The proposed structure is thus very useful for observation, characterization and modeling of static and dynamic transistor variations during switching operation.

Reconfigurable delay cell for area-efficient implementation of on-chip MOSFET monitor schemes

To measure target MOSFET variation, specific monitor schemes are required. With device scaling, developing each monitor scheme is costly. This paper proposes a universal delay monitor cell which enables measurements of various types of variations with single monitor scheme. The monitor cell is reconfigurable and standard cell compatible; thus it can be used in the conventional place and route flow. An area-efficient monitor scheme to monitor global, local, and dynamic variations is developed. Measurement results from a 65-nm test chip shows the validity of the proposed monitor cell. The proposed cell enables area-efficient and low cost implementation of monitor schemes which can be integrated with application such as testing and adaptive voltage scaling.

Characterization and compensation of performance variability using on-chip monitors

Aggressive technology scaling and strong demand for lowering supply voltage impose a serious challenge in achieving robust and energy-efficient circuit operation. This paper first overviews circuit techniques for variability resilience including onchip circuits for performance and variability monitoring. We then focus on on-chip delay cells for transistor performance estimation and homogeneous and inhomogeneous ring oscillators for Die-to- Die (D2D) and Within-Die (WID) variability extraction. We also explain topology-reconfigurable on-chip monitors for in-situ variability characterization which can be used for D2D and WID variability modeling. The monitor can also be used for monitoring temporal variability such as Random Telegraph Noise (RTN). Compensation of performance variability can be done by a localized body biasing with on-chip monitors. A proof-of-concept circuit fabricated in a 65 nm process will be demonstrated such that a test chip fabricated at the slow process corner can achieve a target performance under the typical process condition by the compensation.

A body bias generator with wide supply-range down to threshold voltage for within-die variability compensation

A body bias generator (BBG) for fine-grain body biasing (FGBB) that can operate under wide supply-range is proposed. While FGBB is effective in reducing variability and power consumption, a number of BBGs are required on a die and therefore simplified design of BBGs is necessary. This paper proposes a cell-based design of a BBG that generates forward and reverse body bias voltages only from a core supply voltage ranging from the near threshold of 500mV to the nominal voltage of 1.2V. This wide operating range is achieved by a low voltage error amplifier with a Vth biasing scheme achieved by internal switched-capacitor charge pumping. We fabricated the forward/reverse BBG in a 65nm low power CMOS process to control 0.22mm2 of core circuit with the area overhead of 2.3% for the BBG.

Area-efficient reconfigurable ring oscillator for device and circuit level characterization of static and dynamic variations

Accurate characterization of transistor variation under dynamic switching condition has become important for reliable digital circuit design. This paper proposes a reconfigurable ring oscillator (RO) structure which enables measurement of transistor level variation. Each inverter stage in the RO can be configured into several delay modes. The delay of a particular inverting stage can be made dominant by configuring an inhomogeneous RO structure. By scanning the inhomogeneous stage, delay variation of each stage can be measured. Furthermore, pMOSFET and nMOSFET variation can be measured separately by making only rise or fall delay dominant. Specific transistor with random telegraph noise (RTN) in the inhomogeneous stage can be identified by reconfiguring the inhomogeneous stage. Thus, using a single RO, static delay variation as well as dynamic variation such as RTN can be measured. The area for a 127-staged reconfigurable RO including peripheral circuits is only 0.0085 mm2 thus area-efficient measurement becomes possible. Measurement results from a 65-nm test chip shows the validity of the proposed circuit structure.

Energy reduction by built-in body biasing with single supply voltage operation

Energy-efficiency has become the driving force of todays LSI industry. In order to achieve minimum energy operation of LSI, we propose a built-in body biasing technique which generates independent body biases for nMOSFET and pMOSFET separately. We design and fabricate an application circuit integrated with our proposed built-in body bias generation (BBG) circuits in a 65-nm process. The application circuit consists of AES cipher and decipher modules. The BBG does not require an external supply and it is compatible with a dynamic voltage scaling scheme for the application circuit. Cell-based design of the BBG circuit has been applied to facilitate automatic place and route. Both of the AES and the BBG circuits have been routed simultaneously to reduce design and area overhead. In post-silicon, supply voltage and body bias voltages are selected to achieve the minimum energy consumption for a target frequency. From the measurement results, more than 20% of energy reduction is achieved compared with adjusting supply voltage alone.

A statistical modeling methodology of RTN gate size dependency based on skewed ring oscillators

This paper proposes a statistical modeling methodology of RTN (Random Telegraph Noise) gate size dependency utilizing skewed ring oscillator (RO) structures. An iterative characterization flow is developed to estimate RTN induced threshold distribution of each gate sizes of pMOSFET and nMOSFET independently. The skewed RO based test structure was fabricated in a 65 nm SOTB (Silicon On Thin Body) process. It is observed that Lognormal distribution represents RTN induced delay distribution well. RTN model of gate size dependency is then developed and validated using the measured data. Model based delay distribution estimation and measurement match well. The proposed extraction methodology is thus suitable for estimating RTN of transistors with arbitrary gate size. The model helps reliability and worst case analysis of digital circuits where transistors of various gate sizes are used.

Statistical analysis and modeling of Random Telegraph Noise based on gate delay variation measurement

We propose a characterization and modeling methodology for Random Telegraph Noise (RTN) induced ΔVt_h variation based on gate delay variation measurement. We characterize the total amount of ΔV_th and model its scaling effect. A topology-reconfigurable ring oscillator (RO) is used to obtain gate delay variations between inverter stages. The devices under test are operated at near- or sub-threshold region to characterize RTN at low supply voltage. Measurement and characterization results from a 65 nm test chip show that lognormal distribution based modeling represents RTN-induced ΔV_th variability precisely. We extract the model parameters and evaluate the gate size dependency of these parameters. It is found that μ₁ of the lognormal distribution, lnN(μ₁, σ₁²), does not have specific gate size dependency. Whereas, σ shows a W^-a dependency to gate size rather than the commonly assumed W^-1 dependency, where a is evaluated to be less than 0.5. The proposed comprehensive statistical model and its parameter dependency is suitable for performance analysis of circuits where transistors of different gate sizes are used.

Wide-supply-range all-digital leakage variation sensor for on-chip process and temperature monitoring

Variation in process, voltage and temperature is a major obstacle in achieving energy-efficient operation of LSI. This paper proposes an all-digital on-chip circuit to monitor leakage current variations of both of the nMOSFET and pMOSFET independently. As leakage current is highly sensitive to threshold voltage and temperature, the circuit is suitable for tracking process and temperature variation. The circuit uses reconfigurable inhomogeneity to obtain statistical properties from a single monitor instance. A compact reconfigurable inverter topology is proposed to implement the monitor circuit. The compact and digital nature of the inverter enables cell-based design, which will reduce design costs. Measurement results from a 65 nm test chip show the validity of the proposed circuit. For a 124 sample size for both of the nMOSFET and pMOSFET, the monitor area is 4500 μm2 and active power consumption is 76 nW at 0.8 V operation. The proposed technique enables area-efficient and low-cost implementation thus can be used in product chips for applications such as dynamic energy and thermal management, testing and post-silicon tuning.

Effect of supply voltage on random telegraph noise of transistors under switching condition

For efficient design of digital circuits operating under wide range of voltage voltages, RTN model incorporating the dependencies of both the gate area and supply voltage are required. In this paper, we characterize the delay distributions due to RTN under different supply voltages. The delay distributions are then converted to threshold voltage distributions by statistical analysis. Measurement results from a 65 nm Silicon-on-Thin-Buried-Oxide high performance process reveal that threshold voltage distribution remains almost the same across the supply voltages of 0.4 V to 1.0 V. Furthermore, nMOSFET and pMOSFET ΔΥτ distributions are also estimated to be identical. However, low correlation has been observed between the RTN amplitudes across the supply voltages which is a concern for testing and post-silicon tuning methods.