Jun Shiomi

An energy-efficient on-chip memory structure for variability-aware near-threshold operation

On-chip memory is one of the most energy consuming components in processors. Aggressive voltage scaling to the sub-/near-threshold region is thus applied even to the memory used for ultra-low power applications. In this paper, an energy-efficient cell-based memory structure which is stably working with a near-threshold operating voltage is proposed. The circuit simulation using a commercial 28-nm technology shows that the energy consumption for the readout operation in our memory proposed here is up to 61% less than the energy dissipated in an existing cell-based memory and a conventional SRAM circuit. The simulation using a foundry provided Monte Carlo package also shows that the 3σ worst case read-access time of our cell-based memory is comparable to that of the SRAM circuit.

Fully digital on-chip memory using minimum height standard cells for near-threshold voltage computing

This paper proposes a standard-cell based memory (SCM) as an alternative to a traditional on-chip SRAM for near-threshold voltage computing. It focuses on area- and energy-efficiency using minimum height standard-cells. Unlike conventional SCMs, the proposed SCM has standard-cells with a minimum possible cell height allowed by the logic design rule of the target technology. This paper also presents energy efficient readout and write schemes for reducing dynamic energy consumption. Post layout simulation using 65-nm FDSOI technology shows that the proposed SCM achieves area efficiency of 5.9 μm2 per bit (592F2 per bit), which is less than that of the state of the art SCMs. The results also show that the energy consumption is further improved when the supply voltage scaling and back-gate biasing techniques are applied to our SCM.

A closed-form stability model for cross-coupled inverters operating in sub-threshold voltage region

A cross-coupled inverter which is an essential element of on-chip memory subsystems plays an important role in synchronous LSI circuits. In this paper, an analytical stability model for a cross-coupled inverter operating in a sub-threshold voltage region is proposed. The proposed model analytically shows that the minimum operating voltage of the cross-coupled inverter distributes normally in a high-s region if the distribution of the threshold voltage is Gaussian. The minimum supply voltage at which the yield of the cross-coupled inverter becomes a specific value can be accurately derived by a simple calculation using the model. Monte-Carlo simulation assuming a commercial 28 nm process technology demonstrates the accuracy and the validity of the proposed model. Based on the model, this paper shows strategies for variation tolerant memory design.

Microarchitectural-level statistical timing models for near-threshold circuit design

Near-threshold computing has emerged as a promising solution for drastically improving the energy efficiency of microprocessors. This paper proposes architectural-level statistical static timing analysis (SSTA) models for the near-threshold voltage computing where the path delay distribution is approximated as a lognormal distribution. First, we prove several important theorems that help consider architectural design strategies for high performance and energy efficient near-threshold computing. After that, we show the numerical experiments with Monte Carlo simulations using a commercial 28-nm process technology model and demonstrate that the properties presented in the theorems hold for the practical near-threshold logic circuits.

Wide-supply-range all-digital leakage variation sensor for on-chip process and temperature monitoring

Variation in process, voltage and temperature is a major obstacle in achieving energy-efficient operation of LSI. This paper proposes an all-digital on-chip circuit to monitor leakage current variations of both of the nMOSFET and pMOSFET independently. As leakage current is highly sensitive to threshold voltage and temperature, the circuit is suitable for tracking process and temperature variation. The circuit uses reconfigurable inhomogeneity to obtain statistical properties from a single monitor instance. A compact reconfigurable inverter topology is proposed to implement the monitor circuit. The compact and digital nature of the inverter enables cell-based design, which will reduce design costs. Measurement results from a 65 nm test chip show the validity of the proposed circuit. For a 124 sample size for both of the nMOSFET and pMOSFET, the monitor area is 4500 μm2 and active power consumption is 76 nW at 0.8 V operation. The proposed technique enables area-efficient and low-cost implementation thus can be used in product chips for applications such as dynamic energy and thermal management, testing and post-silicon tuning.

Variability- and correlation-aware logical effort for near-threshold circuit design

Near-threshold computing has emerged as a promising solution for drastically improving the energy efficiency of CMOS circuits. The paper proposes an improved logical effort model that can be used for optimum gate sizing of near-threshold circuits. First, we propose an improved logical effort model which help circuit designers consider not only delay variation but also a correlation between slew rates of adjacent logic gates. To the best of our knowledge, this is the first analytical model that considers not only delay variation of gates but also a correlation between slew rates of adjacent gates. Then, we discuss an analytical approach using the model for minimizing buffer delay. Based on the approach, we develop a gate sizing method which achieves both higher energy efficiency and less delay than the method of logical effort without considering variability and slew correlation. Finally, we show a result with transistor-level circuit simulation using a commercial 28-nm process technology model. Simulation results show that our gate sizing achieves up to 19% smaller delay and 23% smaller energy consumption than a method based on the theory of logical effort without considering variability and slew correlation.