A. Nakagawa

New 1200 V MOSFET structure on SOI with SIPOS shielding layer

In this paper, we have experimentally obtained, for the first time, 1200 V lateral diodes and MOSFETs on SOI. The SOI structure is characterized by a SIPOS layer inserted between the silicon layer and the buried oxide. It was found that the new SOI diode breakdown voltage is determined by the conventional bulk p-n junction theory and not by the resurf (reduced surface field) principle.

Low gate charge 30 V n-channel LDMOS for DC-DC converters

We have developed low on-resistance and low feedback gate charge 30 V n-channel LDMOS for MHz switching DC-DC converter applications. The feature of the device is that it has achieved a high avalanche capability of more than 20 amperes together with Ron/spl dot/Qqd value of 10 m/spl Omega/nC, which is the lowest, ever reported for 30 V devices. A low gate resistance of 0.4 /spl Omega/ was achieved by two layer metal electrodes. These features are desirable for MHz switching frequency DC-DC converters to obtain higher efficiency. Good avalanche capability of 20 amperes is achieved under unclamped inductive switching (UIS) condition.

Improvement in lateral IGBT design for 500 V 3 A one chip inverter ICs

This paper reports, for the first time, the development of 500 V, 3 A single chip inverter ICs. The chip size of the IC is 7.1/spl times/5.2 mm/sup 2/, which is only 30% larger than that of 500 A, 1 A inverter ICs. The chip size reduction has been realized by 35% improvement in lateral IGBT on-resistance and an optimized layout of LIGBT unit cells and bonding pads.

Impact of dielectric isolation technology on power ICs

The impact and advantages of dielectric isolation (DI) are discussed, and the directions of DI research are highlighted. It is noted that DI is a superior method for integrating many kinds of devices in a single chip. The success of a high voltage telecommunication IC, called SLIC, has advanced the technology of DI. It is suggested that the next driving force will be high voltage and relatively large current power ICs, integrating a small power system unit into a single chip. This small-scale version of system-on-chip ICs will fully utilize the advantages of the DI method, operated at a high temperature when installed inside such instruments as motors or lamps. This will realize simplified and small sized power systems or equipment. Research efforts for a low cost DI method will be led by SOI (silicon on insulator) technology using several-micron-thick-or-less silicon layers. This will simplify the device isolation and even attain high voltages.<<ETX>>

Predicted electrical characteristics of 4500 V super multi-RESURF MOSFETs

In this paper, we show the optimized device parameters for various voltage multi-RESURF devices based on exact simulation. In addition, we also present, for the first time, the exact static and transient simulation of a 4500 V multi-RESURF device. The distinguishing feature of the multi-RESURF MOSFET is that a storage time exists and that the fall time is extremely small. The multi-RESURF MOSFET was found to be an ideal device for high voltage applications, superior to IGBTs.

Numerical analysis of SOI IGBT switching characteristics-switching speed enhancement by reducing the SOI thickness

The electrical characteristics of SOI (silicon-on-insulator) IGBTs (insulated-gate bipolar transistors), including breakdown voltage are discussed. It is found that the switching speed of an IGBT on a thin SOI is improved by reducing the SOI layer thickness without special design optimization. Carrier recombination at the Si-SiO/sub 2/ interface is shown to affect carriers as if the bulk lifetime were reduced for a thin SOI, thus further improving the switching speed of IGBTs on thin (2- mu m) SOIs.<<ETX>>

Improved 600 and 1200 V IGBT with low turn-off loss and high ruggedness

A novel 600 and 1200 V IGBT (insulated-gate bipolar transistor) family has been developed for operation at more than 20 kHz with sufficient ruggedness. It was found that turn-off loss can be reduced by optimizing the n/sup -/ layer thickness as well as the n/sup +/ buffer impurity profile. A thick n/sup -/ layer was found to be an important factor in improving device ruggedness. Turn-off loss was successfully reduced to one-third of that in conventional IGBTs, while a large safe operating area was retained.<<ETX>>

Ultra-high di/dt 2500 V MOS assisted gate-triggered thyristors (MAGTs) for high repetition excimer laser system

A novel MOS assisted gate-triggered thyristor (MAGT) having high di/dt turn-on characteristics is proposed. It is shown that 40 kA/cm/sup 2// mu s of di/dt can be attained for a turn-on from 1500-V anode voltage, 9090-A/cm/sup 2/ peak anode current, and 0.7- mu s pulse width, with an extremely low turn-on power loss. The transient anode voltage, caused by high di/dt, is less than 100 V, even in the case of 9090 A/cm/sup 2/ for the anode current density. It is concluded that MAGT is a very promising device to replace thyratrons in a high-repetition excimer laser system.<<ETX>>

High-frequency 6000 V double-gate GTO's

A double-gate gate turn off (GTO) thyristor, which has an additional gate on the n-base layer, has been proposed to realize high-frequency operation for high-power inverters. The double-gate structure has further been combined with an n-buffer structure to realize narrow n-base width. A forward-blocking voltage of 6000 V was obtained, even at 150 degrees C, when the second gate was shorted to the anode electrode. In order to reduce turn-on and turn-off switching losses, the dependence of these losses on a time interval between two gate triggering pulses has been investigated. It was found that the turn-off loss of approximately 1/20th of that for a conventional GTO thyristor was achieved by adjusting the time interval between the two gate triggering pulses. >

Improved 20 V lateral trench gate power MOSFETs with very low on-resistance of 7.8 m/spl Omega//spl middot/mm/sup 2/

We propose an improved lateral trench gate MOSFET with a new trench drain contact. The device is predicted to achieve 25 V breakdown voltage and a very low on-resistance of 7.8 m/spl Omega//spl middot/mm/sup 2/, which is by 20% lower than that of previously proposed standard lateral trench gate MOSFETs. The proposed trench contact uniformly distributes the electron current in the drift layer, and effectively reduces the device on-resistance. In the present paper, we also show the detailed electrical characteristics of the fabricated standard trench gate LDMOS. The large current turn-off capability of 1.1/spl times/10/sup 4/ A/cm/sup 2/ was achieved by the fabricated device.