A. Perez-Pascual

The use of CORDIC in software defined radios: a tutorial

CORDIC is a versatile algorithm widely used for VLSI implementation of digital signal processing applications. This article presents a tutorial of how to use CORDIC to implement different communication subsystems that can be found in a software defined radio. Specifically, it shows how to use CORDIC to implement direct digital synthesizers, AM, PM, and FM analog modulators and ASK, PSK and FSK modulators, up-/down-converters of in-phase and quadrature signals, full mixers for complex signals, and phase detection for synchronizers. The article also shows some tricks to efficiently implement the algorithm

Efficient FPGA implementation of Cordic algorithm for circular and linear coordinates

This paper proposes an efficient FPGA implementation of a common CORDIC architecture for circular and linear coordinates. The proposed circuit is derived from the single coordinate CORDIC architectures and the mapping on the Xilinx slices is fully detailed. Relative placed macros in VHDL have been designed to show the goodness of the proposed architecture. All the circuits have been implemented in Virtex-E and Virtex-II devices and the results show that the area of the common architecture is hardly larger than the area of a single coordinate or single mode CORDIC architecture. It is also shown that if a common architecture is modeled with RTL style its implementation requires the double of area and the maximum throughput decreases more than a half.

Efficient Mapping of CORDIC Algorithm for OFDM-Based WLAN

In an orthogonal frequency division multiplexing-based wireless local area network receiver there are three operations that can be performed by a unique coordinate rotation digital computer (CORDIC) processor since they are needed in different time instants. These are the rotation of a vector, the computation of the angle of a vector and the computation of the reciprocal. This paper proposes a common architecture of CORDIC algorithm suitable to implement the three operations with a reduced increase of the hardware cost with respect to a single operation CORDIC. The proposed architecture has been validated on field programmable gate-arrays devices and the results of the implementation show that area saving around 28% and throughput increment of 64% are obtained.

FPGA-based radix-4 butterflies for HIPERLAN/2

This paper presents two different FPGA-implementation of radix-4 butterflies suitable for HIPERLAN 2. The two approaches lead to an efficient use of the hardware resources available in the target device and reduces the area with respect to the direct implementation of the radix-4 butterfly. Both methods reduce the area required storing the coefficients. The first one uses the symmetries of coefficients for reducing the number of functions to store; the second one takes advantage of the dual-port capability of the embedded block-RAM.

Fully-parallel LUT-based (2048,1723) LDPC code decoder for FPGA

A good trade-off between performance and complexity is achieved if the min-sum algorithm with 2-bit non-uniform quantization is used to decode Low-Density Parity-Check codes. This paper proposes a method to design Variable Node Update (VNU) units based on Look-up tables suitable to design decoders for this algorithm. The method has been developed for the (2048,1723) LDPC code of the IEEE 802.3an standard and fully-parallel architectures have been implemented in a FPGA device. The results show that with the proposed method 35% area saving is achieved with respect to the use of the conventional VNU units.

A 630 Mbps non-binary LDPC decoder for FPGA

A high-speed non-binary LDPC decoder based on Trellis Min-Max algorithm with layered schedule is presented. The proposed approach compresses the check-node output messages into a reduced set, decreasing the number of messages sent to the variable node. Additionally, the memory resources from the layered architecture are reduced. The proposed decoder was implemented for the (2304,2048) NB-LDPC code over GF(16) on a Virtex-7 FPGA and in a 90 nm CMOS process. Our implementation outperforms state-of-the-art NB-LDPC decoder implementations for both technologies, achieving a throughput of 630 and 965 Mbps, respectively.

FPGA-implementation of Time-Multiplexed Multiple Constant Multiplication based on carry-save arithmetic

This paper proposes a method to implement time-multiplexed multiple constant multiplication (T-MMCM) based on carry-save adders on FPGA devices. Some basic cells have been defined. These cells are efficiently mapped on the FPGA devices and allow the designer to built T-MMCM circuits based on a tree topology. The performance of the proposed method has been validated by means of two designs: an n-point FFT butterfly with n=64, 128 and 256, and a 2-D DCT. Both designs have been implemented on a Virtex-5 device. The results show that the proposed method improves the throughput (up to 50%) and reduces the area in many cases compared to the implementation based on carry-propagate adders.

Scheme for Reducing the Storage Requirements of FFT Twiddle Factors on FPGAs

A scheme for reducing the hardware resources to implement on LUT-based FPGA devices the twiddle factors required in Fast Fourier Transform (FFT) processors is presented. The proposed scheme reduces the number of embedded block RAM for large FFTs and the number of slices for FFT lengths higher than 128 points. Results are given for Xilinx devices, but they can be generalized for other advanced LUT-based devices like ALTERA Stratix.

Efficient mapping on FPGA of a Viterbi decoder for wireless LANs

In this paper an optimized hardware implementation on FPGA of a Viterbi decoder is presented for WLAN. A fixed-point analysis is made and its performance is compared with a soft decision decoding floating point model with CSI weight. Only 6 bits are needed to perform the soft quantification and 7 bits to the CSI, in order to maintain the performance of the floating point model. A normalization method is proposed to increase the throughput of the decoder, being possible to decode 172 Mbps when it is implemented in a Virtex 2 device. Power consumption results of the decoder implementation are presented for Hiperlan/2 maximum rate. Moreover, it has been shown that it is possible to reduce the power consumption disabling the unnecessary hardware depending on the WLAN modes.

Distributed arithmetic radix-2 butterflies for FPGA

This paper systematizes the design of radix-2 DIF butterflies for large FFTs based on distributed arithmetic. The butterflies are suitable for FFTs up to 4096 points and have been efficiently mapped on FPGA. Two improvements have been proposed with respect the previously published structures. First, the use of 5-input LUTs allows codifying higher number of angles per stage and does not reduce the throughput. Second, minimum area butterflies are obtained by combining the three methods explained in the paper. In such a case, the performance is increased: the area and the latency are reduced and the throughput is increased.