F. Angarita

Efficient FPGA implementation of Cordic algorithm for circular and linear coordinates

This paper proposes an efficient FPGA implementation of a common CORDIC architecture for circular and linear coordinates. The proposed circuit is derived from the single coordinate CORDIC architectures and the mapping on the Xilinx slices is fully detailed. Relative placed macros in VHDL have been designed to show the goodness of the proposed architecture. All the circuits have been implemented in Virtex-E and Virtex-II devices and the results show that the area of the common architecture is hardly larger than the area of a single coordinate or single mode CORDIC architecture. It is also shown that if a common architecture is modeled with RTL style its implementation requires the double of area and the maximum throughput decreases more than a half.

Reduced-Complexity Min-Sum Algorithm for Decoding LDPC Codes With Low Error-Floor

This paper proposes a low-complexity min-sum algorithm for decoding low-density parity-check codes. It is an improved version of the single-minimum algorithm where the two-minimum calculation is replaced by one minimum calculation and a second minimum emulation. In the proposed one, variable correction factors that depend on the iteration number are introduced and the second minimum emulation is simplified, reducing by this way the decoder complexity. This proposal improves the performance of the single-minimum algorithm, approaching to the normalized min-sum performance in the water-fall region. Also, the error-floor region is analyzed for the code of the IEEE 802.3an standard showing that the trapping sets are decoded due to a slow down of the convergence of the algorithm. An error-floor free operation below BER=10-15 is shown for this code by means of a field-programmable gate array (FPGA)-based hardware emulator. A layered decoder is implemented in a 90-nm CMOS technology achieving 12.8 Gbps with an area of 3.84 mm2.

Statistical power estimation for FPGAs

This article presents a power estimation tool integrated with an FPGA design flow. It is able to estimate total and individual-node average power consumption for combinational blocks. The tool is based on the statistical approach, allowing the user to specify the tolerated error and confidence level of the power estimation. An important feature of this software is the short pulse filtration that leads, in other case, to overestimation. Power maps generation is implemented to help both to detect hot-spots, and perform a power optimization. These maps show the power at every physical position in the die. Several circuits have been tested in order to demonstrate the tool features and usability. The estimated values of dynamic power have been compared with physical measurements for Virtex and Virtex-E devices.

Efficient Mapping of CORDIC Algorithm for OFDM-Based WLAN

In an orthogonal frequency division multiplexing-based wireless local area network receiver there are three operations that can be performed by a unique coordinate rotation digital computer (CORDIC) processor since they are needed in different time instants. These are the rotation of a vector, the computation of the angle of a vector and the computation of the reciprocal. This paper proposes a common architecture of CORDIC algorithm suitable to implement the three operations with a reduced increase of the hardware cost with respect to a single operation CORDIC. The proposed architecture has been validated on field programmable gate-arrays devices and the results of the implementation show that area saving around 28% and throughput increment of 64% are obtained.

Efficient mapping on FPGA of a Viterbi decoder for wireless LANs

In this paper an optimized hardware implementation on FPGA of a Viterbi decoder is presented for WLAN. A fixed-point analysis is made and its performance is compared with a soft decision decoding floating point model with CSI weight. Only 6 bits are needed to perform the soft quantification and 7 bits to the CSI, in order to maintain the performance of the floating point model. A normalization method is proposed to increase the throughput of the decoder, being possible to decode 172 Mbps when it is implemented in a Virtex 2 device. Power consumption results of the decoder implementation are presented for Hiperlan/2 maximum rate. Moreover, it has been shown that it is possible to reduce the power consumption disabling the unnecessary hardware depending on the WLAN modes.

High-throughput FPGA-based emulator for structured LDPC codes

FPGA-based emulators are used to evaluate the LDPC codes performance at low bit error rates (BER). We propose an emulator for structured LDPC codes that takes advantage of the early termination in high signal-to-noise ratios (SNRs), where most of the received frames can be decoded in one iteration. Moreover, the data generation (received frames) was parallelised to avoid bottlenecks when the decoder throughput is maximum. The emulator was implemented on a Virtex-6 device a (2048,1723) RS-Based LDPC code using the normalised-MS algorithm, achieving an average throughput of 1.35 Gbps with a single core and, 5.7 Gbps with 4 cores in a single FPGA device. The achieved throughput is 4 times faster than the state-of-the-art FPGA emulators in the literature.

Low-complexity low-density parity check decoding algorithm for high-speed very large scale integration implementation

This study proposes a new low-complexity decoding algorithm for low-density parity check codes, which is a variation of the offset min-sum algorithm and achieves a similar performance with lower hardware cost. A finite precision study is presented and the hardware cost of the implementation of three very large scale integration architectures is evaluated. As a conclusion, the proposed algorithm achieves similar performance with an area saving of around 18, 10 and 14% for the memory-based partially parallel, fully parallel and sliced message passing implementations, respectively.

POWER CONSUMPTION REDUCTION IN A VITERBI DECODER FOR OFDM-WLAN

WLAN standards make use of different transmission modes to cope with different channel conditions, these modes make use of different modulation constellations and code rates. Data encoding is done with a 64-state convolutional code of rate 1/2, some modes employ this basic rate and others puncture the encoded data to obtain a rate of 3/4. At the receiver, the decision depth needed by the Viterbi decoder is higher for decoding punctured modes than for decoding non-punctured modes, this means that punctured modes need a greater area and, then, they cause a higher power consumption. This fact is used in this letter to reduce the power consumption of the Viterbi decoder when dealing with half-rate code modes, an architecture that disables the unnecessary hardware in the non-punctured modes allows a reduction of 20% in the dynamic power consumption with an area increase of only 1%.

Reduction of power consumption in a Viterbi Decoder for OFDM-WLAN

This letter shows how the dependency between the puncturing of the coding rate and the decision depth needed by the Viterbi decoder can be used in an OFDM-WLAN receiver to reduce the power consumption. In WLAN standards there are different transmission modes, some of them work with a basic rate 1/2 convolutional code, and others with a punctured version of the basic code. As the modes with the punctured code need a higher decision depth than those with the rate 1/2 code, these modes cause a higher power consumption due to the greater area employed. In this letter it is presented an architecture that disables the unnecessary hardware in the rate 1/2 code modes, and thus, the dynamic power consumption can be reduced.