A.Y. Du

N-type Schottky barrier source/drain MOSFET using ytterbium silicide

Ytterbium silicide, for the first time, was used to form the Schottky barrier source/drain (S/D) of N-channel MOSFETs. The device fabrication was performed at low temperature, which is highly preferred in the establishment of Schottky barrier S/D transistor (SSDT) technology, including the HfO/sub 2/ gate dielectric, and HaN/TaN metal gate. The YbSi/sub 2 - x/ silicided N-SSDT has demonstrated a very promising characteristic with a recorded high I/sub on//l/sub off/ ratio of /spl sim/10/sup 7/ and a steep subthreshold slope of 75 mV/dec, which is attributed to the lower electron barrier height and better film morphology of the YbSi/sub 2 - x//Si contact compared with other self-aligned rare earth metal-(Erbium, Terbium, Dysprosium) silicided Schottky junctions.

Phase change random access memory cell with superlattice-like structure

A superlattice-like structure (SLL) incorporating two nonpromising phase change materials was applied to phase change random access memory (PCRAM) cell. A properly designed SLL structure could balance both the phase change speed and stability of a PCRAM. Moreover, SLL PCRAM cells exhibited lower programming current and fast working time of 5ns. The main reason for the excellent performances is due to the much lower thermal conductivity of the SLL material compared to that of bulk materials. The thermal conductivity of eight SLL layers cycle was found to be smaller than 30% of that of single layer material.

Effect of surface NH3 anneal on the physical and electrical properties of HfO2 films on Ge substrate

Metal-oxide-semiconductor capacitors were fabricated on germanium substrates by using metalorganic-chemical-vapor-deposited HfO2 as the dielectric and TaN as the metal gate electrode. It is demonstrated that a surface annealing step in NH3 ambient before the HfO2 deposition could result in significant improvement in both gate leakage current and the equivalent oxide thickness (EOT). It was possible to achieve a capacitor with an EOT of 10.5 A and a leakage current of 5.02×10−5 A/cm2 at 1 V gate bias. X-ray photoelectron spectroscopy analysis indicates the formation of GeON during surface NH3 anneal. The presence of Ge was also detected within the HfO2 films. This may be due to Ge diffusion at the high temperature (∼400 °C) used in the chemical-vapor deposition process.

A TaN-HfO/sub 2/-Ge pMOSFET with NovelSiH/sub 4/ surface passivation

In this letter, we demonstrate a novel surface passivation process for HfO/sub 2/ Ge pMOSFETs using SiH/sub 4/ surface annealing prior to HfO/sub 2/ deposition. By using SiH/sub 4/ passivation, a uniform amorphous interfacial layer is formed after device fabrication. Electrical results show that the HfO/sub 2/ Ge MOSFET with Si-passivation exhibits less frequency dispersion, narrower gate leakage current distribution, and a /spl sim/140% higher peak mobility than that of the device with surface nitridation.

Schottky-barrier S/D MOSFETs with high-k gate dielectrics and metal-gate electrode

This letter presents a low-temperature process to fabricate Schottky-barrier silicide source/drain transistors (SSDTs) with high-/spl kappa/ gate dielectric and metal gate. For p-channel SSDTs (P-SSDT) using PtSi sourece/drain (S/D) , excellent electrical performance of I/sub on//I/sub off//spl sim/10/sup 7/-10/sup 8/ and subthreshold slope of 66 mV/dec have been achieved. For n-channel SSDTs (N-SSDTs) using DySi/sub 2-x/ S/D , I/sub on//I/sub off/ can reach /spl sim/10/sup 5/ at V/sub ds/ of 0.2 V with two subthreshold slopes of 80 and 340 mV/dec. The low-temperature process relaxes the thermal budget of high-/spl kappa/ dielectric and metal-gate materials to be used in the future generation CMOS technology.

Germanium pMOSFETs with Schottky-barrier germanide S/D, high-/spl kappa/ gate dielectric and metal gate

Schottky-barrier source/drain (S/D) germanium p-channel MOSFETs are demonstrated for the first time with HfAlO gate dielectric, HfN-TaN metal gate and self-aligned NiGe S/D. The drain drivability is improved over the silicon counterpart with PtSi S/D by as much as /spl sim/5 times due to the lower hole Schottky barrier of the NiGe-Ge contact than that of PtSi-Si contact as well as the higher mobility of Ge channel than that of Si.

Physical and electrical characteristics of HfN gate electrode for advanced MOS devices

In this letter, the physical and electrical properties of physical vapor deposited (PVD) hafnium nitride (HfN) is studied for the first time as the metal gate electrode for advanced MOS devices applications. It is found that HfN possesses a midgap work function in tantalum nitride (TaN)/HfN/SiO/sub 2//Si MOS structures. TaN/HfN stacked metal-gated MOS capacitors exhibit negligible variations on equivalent oxide thickness (EOT), leakage current, and work function upon high-temperature treatments (up to 1000 /spl deg/C), demonstrating the excellent thermal stability of HfN metal gate on SiO/sub 2/. Our results suggest that HfN metal electrode is an ideal candidate for the fully depleted SOI and/or symmetric double gate MOS devices application.

Electrical characteristics and suppressed boron penetration behavior of thermally stable HfTaO gate dielectrics with polycrystalline-silicon gate

The thermal stability and electrical characteristics of HfTaO gate dielectric with polycrystalline-silicon gate have been investigated. The incorporation of Ta into HfO2 enhances the crystallization temperature of film dramatically. Transmission electron microscopy micrographs confirm that HfTaO with 43% Ta film remains amorphous even after activation annealing at 950°C for 30s, and the formation of low-κ interfacial layer is observably reduced. The capacitance–voltage curve of metal–oxide–semiconductor capacitor using HfTaO gate dielectric fits well with simulated curve, indicating good interface property between HfTaO and substrate. In addition, the boron penetration behaviors of HfTaO films are sufficiently suppressed as manifested by the narrow flat-band voltage shift. The negligible flat-band voltage shift in HfTaO with 43% Ta film is observed and attributed to its amorphous structure after device fabrication.

High mobility and excellent electrical stability of MOSFETs using a novel HfTaO gate dielectric

In this work, we developed a novel Hf-based gate dielectric for MOSFETs with TaN metal gate. By incorporating Ta into HfO/sub 2/ films, significant improvements were achieved in contrast to pure HfO/sub 2/: (1) the dielectric crystallization temperature is increased up to 1000/spl deg/C; (2) interface states density (D/sub it/) is reduced by one order of magnitude; (3) electron peak mobility is enhanced by more than two times; (4) charge trapping and threshold voltage shift is reduced by 20 times, greatly prolonging the device lifetime; (5) negligible sub-threshold swing and G/sub m/ variations under constant voltage stress (CVS).

Minimization of germanium penetration, nanocrystal formation, charge storage, and retention in a trilayer memory structure with silicon nitride/hafnium dioxide stack as the tunnel dielectric

Trilayer structures, consisting of a rapid thermal oxide (RTO) layer (2.5 or 5 nm thick) grown on silicon, a sputtered Ge middle layer (3–20 nm thick), and a 50-nm-thick sputtered silicon oxide capping layer, exhibit significant penetration of Ge atoms into the silicon substrate for devices with the smaller (2.5 nm) RTO thickness, resulting in negligible nanocrystal formation and hence no charge storage or memory effect. The Ge penetration is minimized by replacing the RTO layer with a high dielectric constant (high-κ) silicon nitride/hafnium dioxide stack (grown by metalorganic chemical vapor deposition) having a larger physical thickness but smaller equivalent oxide thickness of 1.9 nm. Results show that the high-κ trilayer structure exhibits better charge storage capability (in terms of a lower program voltage) and better charge retention performance as compared to the RTO trilayer structure.