Aaron Buchwald

An embedded 240-mW 10-b 50-MS/s CMOS ADC in 1-mm/sup 2/

A distributed-gain preamplifier uses averaging to improve resolution by 4 b in differential nonlinearity (DNL) and 2 b in integral nonlinearity (INL) in a flash analog-to-digital converter (ADC). Fabricated in a 0.5-/spl mu/m, triple-metal, single-poly CMOS process, the circuit measures 1.4 mm/spl times/1.4 mm including a bandgap and a sample-and-hold (SH), while the ADC itself occupies 1-mm/sup 2/. At a conversion rate of 50-MS/s the ADC dissipates 170 mW, the SH dissipates 70 mW, and the untrimmed ADC-plus-SH exhibits 54 dB S/(N+D) with a 12-MHz 90% full-scale input.

A quad multi-speed serializer/deserializer with analog adaptive equalization

A quad multi-speed (1.25/1.5625/2.5/3.125Gb/s) serializer/deserializer implemented in 0.25/spl mu/m CMOS technology is described. It uses a 4/spl times/ interleaved sample-and-hold receiver architecture. An analog adaptive receiver equalizer and a linear phase detector are used for clock and data recovery. At 3.125Gb/s, the serializer RMS jitter is 2.4ps. The serializer/deserializer runs error free for 2/sup 31/-1 PRBS data pattern over various length, up to 40-inches, of FR4 PCB trace.

A 3.125Gbps timing and data recovery front-end with adaptive equalization

A 3.125Gbps timing and data recovery front-end is described. Adaptive discrete-time analog forward equalizers implemented in the receiver are used to cancel intersymbol interference. The coefficients in the analog equalizers are continuously adjusted by a digital adaptation loop. To save power, the digital adaptation loop operates at a 32/spl times/ subsample rate. The timing recovery is 2/spl times/ oversampled and uses these equalizers in its path for robust performance in the presence of intersymbol interference. A quad 3.125Gbps transceiver core has been fabricated in a standard 0.18 /spl mu/m CMOS process.