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Dive into the research topics where Myles Wakayama is active.

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Featured researches published by Myles Wakayama.


symposium on vlsi circuits | 2004

A quad multi-speed serializer/deserializer with analog adaptive equalization

Hui Wang; Xicheng Jiang; D. Tam; Felix Cheung; Darwin Cheung; W. Tong; Michael Q. Le; Myles Wakayama; J. Van Engelen; V. Parthasarathy; Howard Baumer; Aaron Buchwald

A quad multi-speed (1.25/1.5625/2.5/3.125Gb/s) serializer/deserializer implemented in 0.25/spl mu/m CMOS technology is described. It uses a 4/spl times/ interleaved sample-and-hold receiver architecture. An analog adaptive receiver equalizer and a linear phase detector are used for clock and data recovery. At 3.125Gb/s, the serializer RMS jitter is 2.4ps. The serializer/deserializer runs error free for 2/sup 31/-1 PRBS data pattern over various length, up to 40-inches, of FR4 PCB trace.


international electron devices meeting | 2013

Nanometer CMOS from a mixed-signal/RF perspective

Myles Wakayama

The demise of mixed-signal and RF circuit design in nanometer CMOS technologies was predicted, analyzed and well documented since the advent of 65nm technologies. [1-3]. Poor device matching, low intrinsic device gains, gate leakage, nonideal and poor quality passives, and myriad reliability constraints, such as electromigration and voltage limitations, have been identified as potential barriers to continued mixed-signal and RF embedded design. Not surprisingly, most of these problems also significantly impact logic gate and memory design. Many design techniques have been proposed to address these issues. The most prominent of these, with the declining cost and improving performance of logic gates, is the use of digital signal processing as a standard practice to correct for nonideal circuit properties such as mismatch, distortion and even noise. This practice has led to significant innovation on many levels, from the direct calibration of active and passive devices [4-8], to complete rearchitecting of entire systems [9-10] to move the analog/digital boundary closer to the inputs. The ongoing challenge is: given exponentially rising manufacturing costs, can continual product-level performance advances be achieved in a cost-competitive way?


Archive | 2004

Phase interpolator device and method

Aaron Buchwald; Myles Wakayama; Michael Le; Josephus Van Engelen; Xicheng Jiang; Hui Wang; Howard Baumer; Avanindra Madisetti


Archive | 2000

Digital IF demodulator for video applications

Pieter Vorenkamp; Myles Wakayama; Steven T. Jaffe; Frank Carr; Arnoldus Venes; Peter R. Kinget; Daniel Marz; Thinh Nguyen


Archive | 2001

System and method for high speed communications using digital signal processing

Oscar E. Agazzi; Gottfried Ungerboeck; Keshab K. Parhi; Christian A. J. Lutkemeyer; Pieter Vorenkamp; Kevin T. Chan; Myles Wakayama


Archive | 1999

Low jitter high phase resolution pll-based timing recovery system

Myles Wakayama; Stephen A. Jantzi; Kwang Young Kim; Yee Ling Felix Cheung; Ka Wai Tong


Archive | 2001

Low offset and low glitch energy charge pump for PLL-based timing recovery systems

Myles Wakayama


Archive | 2002

Phase-interpolator based PLL frequency synthesizer

Chun-Ying Chen; Michael Q Le; Myles Wakayama


Archive | 2004

Frequency division/multiplication with jitter minimization

Siavash Fallahi; Myles Wakayama; Pieter Vorenkamp


Archive | 2004

Dual conversion receiver with reduced harmonic interference

Ramon A. Gomez; Myles Wakayama

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