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Dive into the research topics where Aaron Tsai is active.

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Featured researches published by Aaron Tsai.


Ibm Journal of Research and Development | 2009

Design and microarchitecture of the IBM system z10 microprocessor

Chung-Lung Kevin Shum; Fadi Y. Busaba; S. Dao-Trong; Guenter Gerwig; Christian Jacobi; Thomas Koehler; E. Pfeffer; Brian R. Prasky; J. G. Rell; Aaron Tsai

The IBM System z10™ microprocessor is currently the fastest running 64-bit CISC (complex instruction set computer) microprocessor. This microprocessor operates at 4.4 GHz and provides up to two times performance improvement compared with its predecessor, the System z9® microprocessor. In addition to its ultrahigh-frequency pipeline, the z10™ microprocessor offers such performance enhancements as a sophisticated branch-prediction structure, a large second-level private cache, a data-prefetch engine, and a hardwired decimal floating-point arithmetic unit. The z10 microprocessor also implements new architectural features that allow better software optimization across compiled applications. These features include new instructions that help shorten the code path lengths and new facilities for software-directed cache management and the use of 1-MB virtual pages. The innovative microarchitecture of the z10 microprocessor and notable differences from its predecessors and the IBM POWER6™ microprocessor are discussed.


Archive | 2008

Method and system for handling cache coherency for self-modifying code

Gregory W. Alexander; Christian Jacobi; Barry Watson Krumm; Chung-Lung Kevin Shum; Aaron Tsai


Archive | 2008

Method and system for a multi-level virtual/real cache system with synonym resolution

Barry Watson Krumm; Christian Jacobi; Chung-Lung Kevin Shum; Hans-Werner Tast; Aaron Tsai; Ching-Farn E. Wu


Archive | 2003

System and method for simultaneous access of the same line in cache storage

Mark A. Check; Jennifer A. Navarro; Chung-Lung K. Shum; Timothy J. Slegel; Aaron Tsai


Archive | 2008

METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR HANDLING ERRORS IN A CACHE WITHOUT PROCESSOR CORE RECOVERY

Christian Jacobi; Matthias Pflanz; Chung-Lung Kevin Shum; Hans-Werner Tast; Aaron Tsai


Archive | 2003

Parallel cache interleave accesses with address-sliced directories

Jennifer A. Navarro; Chung-Lung K. Shum; Aaron Tsai


Archive | 2008

METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR CROSS-INVALIDATION HANDLING IN A MULTI-LEVEL PRIVATE CACHE

Ka Shan Choy; Jennifer A. Navarro; Chung-Lung Kevin Shum; Aaron Tsai


Archive | 2008

PROCESSOR AND METHOD FOR STORE DATA FORWARDING IN A SYSTEM WITH NO MEMORY MODEL RESTRICTIONS

Aaron Tsai; Barry Watson Krumm; James R. Mitchell; Bradley S. Nelson; Brian D. Barrick; Chung-Lung Kevin Shum; Michael H. Wood


Archive | 2008

System and method for avoiding deadlocks when performing storage updates in a multi-processor environment

Chung-Lung Kevin Shum; Brian D. Barrick; Aaron Tsai; Charles F. Webb


Archive | 2010

MANAGING CACHE COHERENCY FOR SELF-MODIFYING CODE IN AN OUT-OF-ORDER EXECUTION SYSTEM

Christian Jacobi; Brian R. Prasky; Aaron Tsai

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