Abdelhalim Slimane

A Novel Design Method for Compact UWB Bandpass Filters

In this letter, a new design method of ultra wideband bandpass filter (UWB BPF) is proposed. Based on a symmetrical structure of a simple uniform line loaded by a stepped-impedance open stub (SIS) connected at its center, the proposed design method employs simultaneously the optimization of a defined objective function in the range of frequency 3.1-10.6 GHz and the transmission zeros at cut-off frequencies for a rapid convergence. Obtaining different filter sizes with good performance, the compact UWB BPF is simulated, fabricated, and measured. A good agreement between simulation and measurement is obtained while achieving good performances such as a return loss better than 10 dB, an upper stopband attenuation higher than 20 dB up to 17.6 GHz, and a sharp selectivity.

Low power and high linear reconfigurable CMOS LNA for multi-standard wireless applications

This paper presents a low power and high linear reconfigurable CMOS low noise amplifier for wireless multi-standard applications including GSM (PCS1900), 3G (UMTS), Bluetooth and WLAN b/g. Based on inductive degenerated cascode topology, this LNA achieves a good trade-off between high gain, noise figure and power consumption. The input and output matching networks include controlled MOS-varactor devices to select the desired bands for multi-standard purpose. A post linearization technique is also used to improve the LNA linearity. Implemented in 0.18-μm CMOS technology, the simulated results perform a power gain higher than 21 dB, a noise figure below 2.7 dB, an input return loss less than -12.1dB and more than -3 dBm for the third-order input intercept point in frequency band 1.9-2.4 GHz. For all standards the proposed LNA consumes only a 10.9mW from 1.8V supply voltage.

High Speed Low Power CMOS Comparator for Pipeline ADCs

This paper describes and analyzes a low power and high speed differential comparator. The designed comparator is intended to be implemented in a 10bit 20MHz pipeline analog-to-digital converter dedicated to RF WLAN applications. This comparator is based on the switched capacitor network using a two-phase nonoverlapping clock. The offset voltage of the designed comparator has been reduced by means of an active positive feedback. The analyses and simulation results which have been obtained using 0.8mum CMOS AMS process parameters, with a power supply voltage of 5V and an input common mode of 2-3V, show that this comparator exhibits a propagation delay of 17.3ns, a good accuracy and a low power consumption of about 0.8mW

Design of an optimal layout RF passive polyphase filter for large image rejection

This article presents the design and implementation of a multi-stage radio-frequency (RF) passive polyphase filter (PPF). The layout parasitics and mismatch which deteriorate significantly the RF filter performance are analyzed and modeled. To reduce this parasitic degradation, a novel optimal layout technique is proposed. It is based on reproducing the same optimized PPF stage layout for the different stages while the desired bandwidth is ensured due to an optimal sizing of the inter-stages connections. This approach has been validated with on chip measurements. Using the proposed techniques more than 55 dB of image rejection over the [1.5; 3.3] GHz bandwidth is demonstrated while achieving zero power consumption and small silicon area in 130nm CMOS technology.

Bandwidth enhancement for 0.18 µm CMOS transimpedance amplifier circuit

In this paper, a low noise and high bandwidth transimpedance amplifier (TIA) is designed for optical receiver using a 0.18 μm standard in CMOS technology. The proposed circuit operates at a data rate of 13.25 Gb/s. Employing a series inductive peaking technique, an improvement of bandwidth by only one inductor within the structure is achieved to reach a wide bandwidth of 9.28 GHz. The gain of this amplifier is 53 dB at 9.28 GHz and its input current noise is about 36.12 pA/√Hz.

A 0.9 V high gain and high linear bleeding CMOS mixer for wireless applications

In this paper, a double balanced bleeding CMOS mixer topology, appropriate for low voltage applications, is presented. A low voltage mixer is designed with high gain and good linearity. The bleeding technique and derivative technique are used to make this trade off. The mixer is designed in 0.18 μm CMOS technology and simulated with Spectre RF at 2 GHz input frequency which can work with supplies as low as 0.9 V. The simulation results show the conversion gain of 18 dB, an input referred third order (IIP3) of 9 dBm, input-referred second-order intercept point (IIP2) of +64 dBm, DSB noise figure of 11 dB and 7 mW power dissipation.

A 0.6-V/1.2-V low power single ended CMOS LNA for multi-standard RF front-ends

This paper presents a design of a low power single ended CMOS LNA for reconfigurable applications including GPS, GSM (DCS1800, PCS1900), 3G (UMTS), WLAN b/g and LTE. Based on a wideband input matching, the LNA stages cover all band of interest while achieving a good trade-off between high gain, low noise figure and low power consumption. For multi-standard aim, the LNA selects the desired bands using a high output resonant impedance with a switching technique. Implemented in 0.13-μm CMOS technology, the simulated LNA results at Vdd = 1.2 V perform a power gain higher than 30 dB, a noise figure below 2.3 dB, an input return loss less than -12 dB, and an IIP3 better than -19 dBm in frequency band 1.5-2.6 GHz. Besides, for the low mode at Vdd = 0.6 V, the power gain is better than 19 dB and the noise figure is about 2.9 dB. For all mentioned standards, the proposed LNA consumes 7.5 mW and 2.7 mW from supply voltage of 1.2 V and 0.6 V, respectively.

RF and non-linearity characterization of porous silicon layer for RF-ICs

Nanostructured porous silicon is very promising for RF applications by overcoming the high-frequency losses originating from the bulk silicon substrate. RF performance and non-linearity analysis of different silicon substrates including, porous (PSi), trap-rich (TR) high resistivity (HR) types are explored experimentally. The investigation is done by means of coplanar transmission lines (CPW) fabricated on these substrates. RF measurements of transmission lines demonstrate the successful reduction of the permittivity and increase of the resistivity of the PSi substrate. It also demonstrated that the insertion losses and linearity are efficiently enhanced.

Design and Analysis of CMOS RCG Transimpedance Amplifier Based on Elliptic Filter Approach

This study presents a new design of compact transimpedance amplifier (TIA) for optical communication applications. By adopting the regulated common gate (RCG) topology, the proposed amplifier is designed and synthesised based on a third-order elliptic filter approach. Implemented in 0.13 μm complementary metal oxide semiconductor technology, the post layout simulation results provide 50 dB Ω of direct current gain, 15 GHz of bandwidth, 20 pA/√Hz as an input referred noise current performance. The proposed RCG TIA occupies a 19 × 36 μm 2 while consuming 5.34 mW under 1.2 V supply voltage, only.

Design of high speed transimpedance amplifier for optical communication systems

This paper presents a low noise and high bandwidth transimpedance amplifier (TIA) for optical receiver, operating at data rate of 10 Gb/s. The first configuration of the amplifier which is the basic structure is based on push-pull inverter with resistor in feedback. However, the second configuration employs an inductor in series with a resistor in the feedback to extend the bandwidth and reduce the effect of parasitic capacitances. To optimize the input referred noise of the final design, an active device is used to replace the feedback resistor. Using 0.18 µm CMOS technology, simulation results for optimized structure show a bandwidth of 7.9 GHz, transimpedance gain of 50.8 dBΩ, and input referred noise current of 7.4 pA/√Hz.