Hervé Barthélemy

A 9-pJ/Pulse 1.42-Vpp OOK CMOS UWB Pulse Generator for the 3.1–10.6-GHz FCC Band

This paper presents the design of a fully integrated ultra-wideband (UWB) pulse generator for the Federal Communications Commission (FCC) 3.1-10.6-GHz band. This generator is reserved for medium rate applications and achieves pulses for an on-off keying (OOK) modulation, pulse position modulation, or pulse interval modulation. This UWB transmitter is based on the impulse response filter method, which uses an edge combiner in order to excite an integrated bandpass filter. The circuit has been integrated in an ST-Microelectronics CMOS 0.13-¿m technology with 1.2-V supply voltage and the die size is 0.54 mm2. The pulse generator power consumption is 9 pJ per pulse and achieves a peak to peak magnitude of 1.42 V. The pulse is FCC compliant and the generator can be used with a rate up to 38 Mbs-1 with an OOK modulation. Based on the FCC power spectral density limitation, a sizing method is also presented.

High-Voltage-Gain CMOS LNA For 6–8.5-GHz UWB Receivers

The design of a fully integrated CMOS low noise amplifiers (LNA) for ultra-wide-band (UWB) integrated receivers is presented. An original LC input matching cell architecture enables fractional bandwidths of about 25%, with practical values, that match the new ECC 6-8.5-GHz UWB frequency band. An associated design method which allows low noise figure and high voltage gain is also presented. Measurements results on an LNA prototype fabricated in a 0.13-mum standard CMOS process show average voltage gain and noise figure of 29.5 and 4.5 dB, respectively.

RF Low-Pass Design Guiding Rules to Improve PCB to Die Transition Applied to Different Types of Low-Cost Packages

We present in this paper some design rules to improve the signal integrity (SI) of a package transition. The design rules are based on standard low-pass (LP) filter synthesis methodology. This methodology uses the modeling of the package transition by a pi network and is valid as long as the through phase shift of the package transition remains sufficiently small. Based on this pi network approximation, it is possible to add external distributed elements at the package carrier level and lumped elements at the DIE level to build an equivalent low-pass ladder filter. This approach improves significantly the signal integrity properties of the package transition without modifying the package. In some cases the frequency bandwidth for which the return loss (RL) remains higher than 20 dB can be doubled by using this method.

On-Chip Voltage Regulator Protecting Against Power Analysis Attacks

The on-chip voltage regulator proposed in this paper has been specifically developed for smart cards. Its purpose is to protect the supplied system against power analysis attacks. It allows to generate the internal power supply voltage from the external power supply voltage provided by card readers, while ensuring the uncorrelation between the external power supply current and the internal power supply current. The power supply current of an electronic system can be decomposed into a DC component, which contains little information, and an AC component, which handles considerably more. In order to reach a good compromise between regulation and security, while respecting the smart card stringent technological constraints, these two components are treated separately by a bi-channel power structure. The presented implementation has been simulated from the process parameters of a STMicroelectronics 0.18 mum CMOS technology. It allows to generate a 1.8 V output voltage from a 2 to 5.5 V input voltage range. The structure has been sized to handle a 25 mA DC current while hiding a 20 MHz AC current presenting 75 mA peaks. Its estimated area is approximatively 0.8 mm2.

High speed voltage follower for standard BiCMOS technology

A new wideband low-distortion class A unitary gain voltage follower is presented in this brief. Based on a Gilberts translinear loop of four transistors, the proposed topology only includes high frequency n-p-n transistors in signal paths. The circuit has been simulated under /spl plusmn/1.5 V using the 0.8-/spl mu/m BiCMOS technology from AMS. Simulation results confirm low output distortion and high frequency operation performances. For a total power consumption of only 3 mW, the -3-dB bandwidth of the voltage transfer function is higher than 2.5 GHz with a 1-k/spl Omega/ loading resistance. The corresponding total harmonic distortion rate is lower than 0.06% when a 100-mV peak-to-peak input sinusoidal voltage is applied.

A reconfigurable inductor-less CMOS low noise amplifier for multi-standard applications

This paper presents a reconfigurable inductor-less CMOS low noise amplifier (LNA) for multi-standard wireless applications. The LNA is designed to address PCS1900, UMTS, WLANb/g and Bluetooth frequency bands. The LNA is based on two cascaded stages. The first stage is a resistive feedback amplifier which achieves a wideband matching in order to address the different application frequency bands while performing a low noise figure. The second stage is a cascode amplifier with an active output LC resonator in order to select the desired bandwidth while achieving high gain and low surface area. The proposed multi-standard LNA, implemented in a 0.13μm CMOS technology achieves more than 26dB gain from 1.8 to 2.4GHz for a noise figure less than 3.4dB. The input and output return losses S11 and S22 are lower than -12dB and -16dB respectively. The LNA consumes 9.6 mA from 1.2V supply voltage and occupies a chip area of 0.165mm2 including pads.

A temperature compensated CMOS ring oscillator for wireless sensing applications

This paper presents a CMOS voltage controlled ring oscillator (VCO) with temperature compensation circuit suitable for low-cost and low-power wireless sensing applications. To operate at low frequency, a control voltage generated by a CMOS bandgap reference (BGR) is described and the measurement results of the fabricated chips are presented. The output voltage of the reference is set by resistive subdivision. In order to achieve small area and low power consumption, n-well resistors are used. This design features a reference voltage of 1V. The chip is fabricated in AMS 0.35 µm CMOS process with an area of 0.032mm2. Operating at 1.25V, the output frequency is within 200±l0kHz over the temperature range of −25°C to 80°C with power consumption of 810µW.

Design of a wide tuning range VCO using an active inductor

This paper presents a wide tuning range CMOS voltage controlled oscillator suitable for radio frequency operation. The major advantage of this structure is the absence of on-chip inductor, thus reducing significantly the chip area. Measurements results using a 0.35 mum CMOS process from AMS have shown a wide tuning range of 84% of the 915 MHz central frequency and a phase noise around -90 dBc/Hz at 500 kHz offset from the carrier. The power consumption is reduced to less than 10 mW from a 3.3 V supply.

A new oscillator-based Random Number Generator

This paper proposes a low power, Truly Random Number Generator (TRNG) intended for a RFID tag application. We present here a new approach of the oscillator-based TRNG. The circuit relies on a system of jittered clocks that are being monitored by a clock arbiter-synchroniser, in order to have a random output signal without the use of a high speed jittered oscillator technique, that implies a significative increase the total power budget and a reduction in the output frequency. The system under study will be developed in AMS 0.35μm standard process for a 3.0V supply.

A low power consumption CMOS differential-ring VCO for a Wireless Sensor

This paper describes a three-stage Voltage Controlled ring Oscillator (VCO) based on 0.35 μm CMOS standard technology. The VCO was designed for a transmitter operating in the 863–870 MHz European band for Wireless Sensor applications. A voltage VCTRL controls the oscillation frequency of the VCO. Simulation results of the fully differential VCO with positive feedback show that the estimated power consumption, at desired oscillation frequency and under a supply voltage of 3.3 V, is only 7.48 mW. The proposed VCO exhibits a phase noise lower than −126 dBc/Hz at 10 MHz offset frequency.