M. Si Moussa

Silicon-on-insulator for high-temperature applications

The silicon-on-insulator (SOI) CMOS technology is one of the best candidates for high-temperature applications due to its low leakage current, steep subthreshold slope, absence of latch-up phenomenon and temperature-resistant threshold voltage. However, the most critical elements for high temperature applications are transmission lines, especially thin-film microstrip lines. In the paper, the impact of high-temperature operation on the RF performance of some SOI circuits is analysed up to 250 degrees C.

Low power 23-GHz and 27-GHz distributed cascode amplifiers in a standard 130nm SOI CMOS process

Two fully integrated distributed amplifiers (DA) were designed using a standard 130 nm partially-depleted silicon-on-insulator CMOS process. They make use of either body-contacted (BC) or floating-body (FB) MOSFETs, and microstrip lines. The BC-DA has a 5.4 dB gain and a unity-gain bandwidth of 23 GHz whereas the FB-DA has a 6.8 dB gain and a unity-gain bandwidth of 27 GHz. The measured output power at 1 dB compression is 5 dBm at 5 GHz and the noise figure is 6.5-7.5 dB over 6-18 GHz for both DAs. Power consumption is 58 mW at 1.4 V.

Body-Biasing Control on Zero-Temperature-Coefficient in Partially Depleted SOI MOSFET

This work investigates the possibility to tune the zero-temperature-coefficient (ZTC) points in partially depleted (PD) SOI nMOSFET technology by controlling the body-source forward bias (VBS). Measured transconductance and drain current in the saturation region at temperatures between 25 and 200degC were observed for various body-source forward bias conditions. It is found that the variation of threshold voltage (VTH) with body bias has an influence on ZTC points. The measurement results show wide voltage-range of gate-voltage giving either the transconductance ZTC point (VGS,ZTC9m) or the drain-current ZTC point (VGS,ZTC1DS) opening important opportunities in RF circuits design for nigh temperature applications.

Temperature effect on the performance of a traveling wave amplifier in 130 nm SOI technology

The behavior of an integrated traveling wave amplifier (TWA), fabricated in a 130 nm silicon-on-insulator (SOI) CMOS process, has been characterized over a temperature range from 25/spl deg/C to 250/spl deg/C. The TWA is a four-stage cascode design which uses floating body (FB) transistors and microstrip lines as passives. A gain of 7 dB with a 0.4-27 GHz bandwidth is measured under 1.4 V supply voltage. The effects of high temperature are observed on the gain of the TWA, as well as on the SOI transistors and the microstrip lines.

A 2-mW Power Consumption Low Noise Amplifier in PD SOI CMOS Technology for 2.4 GHz Applications

This paper reviews and analyzes a fully integrated low-noise amplifier (LNA) for low-power and narrow-band applications using a cascode inductive source degeneration topology, with a body contacted transistor in 130 nm partially depleted CMOS SOI technology. Thanks to the SOI technology, the LNA shows only 2 mW power consumption when power gain of 10 dB and a noise figure of 3.1 dB at 2.4 GHz are measured for 1.2 V supply voltage

Design of a Distributed Amplifier with On-chip ESD Protection Circuit in 130 nm SOI CMOS Technology

A fully integrated common source distributed amplifier (CSDA) with ESD protection, designed and fabricated in 130 nm SOI CMOS technology, is presented. This CSDA requires a chip area of 0.75 mm2 . A gain of 4.5 dB and a unity-gain bandwidth of 30 GHz are measured at 1.4 V supply voltage with a measured power consumption of 66 mW. Low capacitance diode is used for electrostatic discharge (ESD) protection for the RF input pin without altering the original design of the CSDA. The CSDA has an ESD protection level up to 1.45 A transmission line pulse (TLP) current, corresponding to 2 kV human body model (HBM) stress

An investigation of temperature effects on CPW and MSL on SOI substrate for RF applications

Losses of microstrip line and coplanar waveguide made on HR and STD SOI wafers were analyzed with respect to temperature. MSL allows the use of STD substrate because the back ground plane shields the Si substrate. MSL can then be an interesting topology if the losses can be lowered to the same level than CPW made on HR SOI or SOS. For the CPW, the losses are of two kinds: conductor losses, due to the metal resistivity, and substrate losses, due to the coupling between the line and the substrate. These results demonstrate the feasibility and practical applicability of different passive structures in circuits design for both room and high temperature applications. Due to the rapid increase in the number of metallic interconnects, the top level metals are situated further away from the SOI substrate as the technology scales, thus reducing the substrate losses for CPW and widen the metallic strip for MSL. In a near future, 12 metal levels are available and enable using 5 times wider strips for MSL and thus reduce the losses by a factor of 3 making MSL as a very promising structure for RF design for the next technological node.

CMOS compatible 3-D self assembled microstructures using thin film SOI technology

3D self-assembled microstructures are processed based on thin film SOI wafers. Self assembled structures going from meander inductors to flow sensors are obtained from using only one photolithographic step. The assembly of our microstructures relies on the thermal expansion mismatch between the material layers as well as control of the plastic flow of one of the layers.

Design of a Distributed Oscillator in 130 nm SOI MOS Technology

In this paper, the design and the results of a silicon-on-insulator (SOI) CMOS distributed amplifier (DA) and oscillator are presented. The four stage cascode DA (CDA) is designed with a 130 nm SOI floating body n-MOSFET in each stage requiring a chip area of 0.75 mm2. A gain of 7 dB and a unity-gain bandwidth of 26 GHz are measured at 1.4 V supply voltage with a measured power consumption of 54 mW. The CDA circuit has been extended to design a cascode distributed oscillator (CDO) showing a 3 dBm carrier at 10 GHz oscillating frequency, for 2.5 V supply voltage

Behavior of a traveling-wave amplifier versus temperature in SOI technology

In this paper, the design and measurement results of a CMOS partially depleted silicon-on-insulator (SOI) traveling-wave amplifier (TWA) are presented. The four-stage TWA is designed with a single common source nMOSFET in each stage using a 130-nm SOI CMOS technology requiring a chip area of 0.75 mm2. A gain of 4.5 dB and a unity-gain bandwidth of 30 GHz are measured at 1.4-V supply voltage for a power consumption of 66 mW. The designed circuit has been characterized over a temperature range from 25 degC to 300 degC. The performance degradation on the gain of the TWA, the SOI transistors, as well as the microstrip lines used for the matching network are analyzed. Thanks to the introduction of a dynamic threshold-voltage MOSFET, a greater gain-bandwidth product under lower bias conditions is demonstrated