Abhijit Pethe

Ge-Interface Engineering With Ozone Oxidation for Low Interface-State Density

Passivation of Ge has been a critical issue for Ge MOS applications in future technology nodes. In this letter, we introduce ozone oxidation to engineer Ge/insulator interface. Density of interface states (D_it) across the bandgap and close to the conduction band edge was extracted using conductance technique at low temperatures. D_it dependence on growth conditions was studied. Minimum D_it of 3 times 10¹¹ cm^-2V^-1 was demonstrated. Physical quality of the interface was investigated through Ge 3d spectra measurements. We found that the interface and D_it are strongly affected by the distribution of oxidation states and the quality of the suboxide.

Ge (100) and (111) N- and P-FETs With High Mobility and Low-

In this paper, we demonstrate high-mobility bulk Ge N- and P-FETs with GeON gate dielectric. The highest electron mobility to date in Ge is reported, and two times improvement over universal hole mobility is achieved for Ge P-FETs. For the first time, the effect of surface orientation on Ge mobility is investigated experimentally. A 50% improvement in electron mobility is shown for the (111) substrate orientation compared to the (100) orientation. Carrier scattering mechanisms are studied through low-temperature mobility measurements and interface characterization. The conductance technique is applied at low temperatures for complete mapping of the density of interface traps (Dit) across the Ge bandgap and also close to the band edges. Carrier scattering mechanisms and the distribution of Dit are compared for Ge NMOS and PMOS.

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Channel materials with high mobility are needed for future nodes to meet the ITRS requirements of MOSFETs. In this work we assess the performance of Si, Ge, and III-V materials like GaAs, InAs and InSb which may perform better than even very highly strained-Si

Mobility Characterization

The performance limits of ultra-thin body double-gated (DG) III-V channel MOSFETs are presented in this paper. An analytical ballistic model including all the valleys (Gamma-, X- and L-), was used to simulate the source to drain current. The band-to-band tunneling (BTBT) limited off currents, including both the direct and the indirect components, were simulated using TAURUSTM. Our results show that at significantly high gate fields, the current in the III-V materials is largely carried in the heavier L-valleys than the lighter Gamma-valleys, due to the low density of states (DOS) in the Gamma, similar to current conduction in Ge. Moreover, these high mobility materials like In As, InSb and Ge suffer from excessive BTBT which seriously limits device performance. Large bandgap III-V materials like GaAs exhibit best performance due to an ideal combination of low conductivity effective electron mass.

High Mobility Materials and Novel Device Structures for High Performance Nanoscale MOSFETs

The highest electron mobility to-date in Ge is reported. For the first time, the effect of surface orientation on mobility is investigated experimentally. Carrier scattering mechanisms are studied through low temperature mobility measurements. Ozone-oxidation has been introduced to engineer Ge/insulator interface. Minimum density of interface states (DD_it) of 3x10¹¹ cm^-2 V^-1 is demonstrated and D_it across the bandgap is extracted.

Investigation of the performance limits of III-V double-gate n-MOSFETs

We propose a novel semiconductor optoelectronic switch that is a fusion of a Ge optical detector and a Si metal-oxide semiconductor field-effect transistor (MOSFET). The device operation is investigated with simulations and experiments. The switch can be fabricated at the nanoscale with extremely low capacitance. This device operates in telecommunication standard wavelengths, hence providing the surrounding Si circuitry with noise immunity from signaling. The Ge gate absorbs light, and the gate photocurrent is amplified at the drain terminal. Experimental current gain of up to 1000x is demonstrated. The device exhibits increased responsivity (approximately 3.5x) and lower off-state current (approximately 4x) compared with traditional detector schemes.

Interface-Engineered Ge (100) and (111), N- and P-FETs with High Mobility

It is believed that to continue the scaling of silicon CMOS innovative device structures and new materials have to be created in order to continue the historic progress in information processing and transmission. Recently germanium has emerged as a viable candidate to augment Si for CMOS and optoelectronic applications. In this work we will first review recent results on growth of thin and thick films of Ge on Si, technology for appropriate cleaning of Ge, surface passivation using high-� dielectrics, and metal induced crystallization of amorphous Ge and dopant activation. Next we will review application of Ge for high performance MOSFETs. Innovative Si/Ge MOS heterostructures will be described with high on current and low off currents. Finally we will describe optical detectors and modulators for on-chip and off-chip interconnect. Successful integration of Ge on Si should allow continued scaling of silicon CMOS to below 22 nm node.

SiGe optoelectronic metal-oxide semiconductor field-effect transistor

We have built high performance PMOSFETs on Si substrates using a Si/Ge/Si heterostructure channel and NiSi source/drain regions. These devices exhibit ~2X improvement in mobility and orders of magnitude increase in the drive current without adversely affecting the OFF state leakage. In conclusion, using a thin Ge layer within the inversion region of a Schottky Si - PMOSFET provides for higher hole mobility (~2X) and much higher drive currents due to almost zero barrier height to holes in the channel. Also the OFF state leakage is maintained at a low value because it is limited by the large barrier height in the wider bandgap Si and Ge quantization. The transistor hence, combines the advantages of high mobility, and low parasitic resistance and is an attractive candidate for scaling PMOSFETs into the sub-20nm regime.

Germanium for High Performance MOSFETs and Optical Interconnects

In this paper, we present a self-consistent, analytical model that includes carrier quantization; short channel effects (SCE) and calculates the ballistic currents in DGFETs. We use this new tool to compare the effect of SCE and process induced variations (PIV) on Silicon (Si) and Germanium (Ge) NMOS DGFETs. Our results show that in the case of DGFETs designed to meet the ITRS High Performance (HP) requirements, even with PIV, Ge performs better than Si. Whereas, due to its poorer SCE, in the case of DGFET designed to meet the ITRS Low Standby Power (LSTP) requirements, Ge performs worse than Si.

High - Mobility, Low Parasitic Resistance Si/Ge/Si Heterostructure Channel Schottky Source/Drain PMOSFETs

A novel, high performance optoelectronic switch is introduced. The device is a Si-MOSFET with Ge gate that can be fabricated at the nanoscale with very low capacitance. Current gain of up to 1000times is demonstrated.