Tejas Krishnamohan

On the Correct Extraction of Interface Trap Density of MOS Devices With High-Mobility Semiconductor Substrates

ldquoConventionalrdquo techniques and related capacitance-voltage characteristic interpretation were established to evaluate interface trap density on Si substrates. We show that blindly applying these techniques on alternative substrates can lead to incorrect conclusions. It is possible to both under- and overestimate the interface trap density by more than an order of magnitude. Pitfalls jeopardizing capacitance-and conductance-voltage characteristic interpretation for alternative semiconductor MOS are elaborated. We show how the conductance method, the most reliable and widely used interface trap density extraction method for Si, can be adapted and made reliable for alternative semiconductors while maintaining its simplicity.

Germanium for High Performance MOSFETs and Optical Interconnects

It is believed that to continue the scaling of silicon CMOS innovative device structures and new materials have to be created in order to continue the historic progress in information processing and transmission. Recently germanium has emerged as a viable candidate to augment Si for CMOS and optoelectronic applications. In this work we will first review recent results on growth of thin and thick films of Ge on Si, technology for appropriate cleaning of Ge, surface passivation using high-� dielectrics, and metal induced crystallization of amorphous Ge and dopant activation. Next we will review application of Ge for high performance MOSFETs. Innovative Si/Ge MOS heterostructures will be described with high on current and low off currents. Finally we will describe optical detectors and modulators for on-chip and off-chip interconnect. Successful integration of Ge on Si should allow continued scaling of silicon CMOS to below 22 nm node.

Multi-Layer High-K Tunnel Barrier for a Voltage Scaled NAND-Type Flash Cell

Low-voltage program/erase (P/E) operations of a NAND-type flash cell have been demonstrated using a multi-layer tunnel barrier. The concept is to achieve low voltage P/E operations similar to a scaled tunnel barrier without compromising retention by exploiting a multi-layer tunnel oxide consisting of a low-k, high-k and low k material. In this study, barrier engineered tunnel oxides of SiO 2 -HfO x -SiO 2 and SiO 2 - ZrOx-SiO 2 were explored using a Metal-Insulator-Nitride-Oxide- Silicon (MINOS) capacitor with a TiN gate electrode. The device programmed/erased at 16/-22 V for 1 ms and it had a memory window of 6 V. The cell showed less than 2 V charge loss after 27 hours when programmed to a 5 V initial window. The proposed high-K tunnel barrier is a promising alternative for tunnel oxide for sub-35 nm NAND Flash technology.

Investigation of Strained-Sb Hetrostructures with High Hole Mobility

Background: III-V semiconductors are one of the most promising device candidates for future high-speed, low-power logic applications due to their high electron mobility. Recently, high performance III-V n-FETs have been demonstrated [1]. However, for CMOS logic, there is a significant challenge of identifying high mobility III-V p-FET candidates [2]. Biaxial strain can be easily introduced in III-V hetrostructures during MBE growth. Biaxial strain splits the degeneracy between light hole (lh) & heavy hole (hh) bands reducing the transport effective mass (m*) and number of states available for interband scattering thereby enhancing hole mobility (μh). Percentage of strain induced (%), Valence Band Offset (VBO) for confining the 2 Dimensional Hole Gas (2DHG), modulation doping, dominant scattering limiting μh , reduction of m* with strain are some of the parameters that need to be investigated for achieving high hole mobilities in III-Vs.

Session 34: Memory technology - nanoscale poly-FG and charge trap flash non-volatile memories

This session will discuss papers related to nanoscale poly floating-gate and charge trap non-volatile memories. The first two papers are on poly-floating gate technologies, the next three are on charge-trap flash memories and the last two are on 3-D NAND flash memories. In the first paper, Toshiba Corporation reports a floating-gate multi-level NAND flash memory technology scalable to 30nm and beyond technology nodes. In the second paper, Qimonda and the Technical University of Munich present a stochastic model of the program operation in scaled NAND flash memories for investigating the interactions between the memory cell and the memory system. Charge-Trap Flash: The next paper by Numonyx and Politecnico di Milano investigates the Random Telegraph Noise scaling trend for both NAND and NOR flash memories. The fourth paper by Toshiba Corporation presents the scalability of a bulk planar SONOS flash memory with double-tunnel junctions down to 10nm gate length. The next paper by National Tsing Hua and Chiao-Tung University reports a new charge-trap engineered non-volatile memory device with very good memory window and high-temperature data retention. 3-D SONOS Flash: In the fifth paper, Schiltron Corporation presents a novel 3-D stackable high-density flash technology, which combines the smallest TFTs to date in series with strings up to 64 cells in a unique architecture to effectively remove pass disturbs. The last paper by Toshiba Corporation, demonstrates a four NAND string 3-D bit cost scalable flash memory with improved program, erase and disturb operation.