Abraham Yoo

A Low-Voltage Lateral SJ-FINFET With Deep-Trench p-Drift Region

A novel device structure that is suitable for practical implementation of lateral superjunction FINFET (SJ-FINFET) on a silicon-on-insulator platform is proposed for sub-200-V rating power applications. The SJ-FINFET structure with heavily doped alternating U-shaped n/p pillars is introduced to minimize both channel and drift resistances and to mitigate electron current crowding near the top of n-drift region. The proposed device structure exhibits low R on, sp with voltage ratings below 200 V. The optimal device characteristics were validated by a 3-D numerical device simulator, ISE-DESSIS. The simulations with trench depths of 2 and 3 mum were analyzed for several different drift lengths and found to be able to overcome the Si limit with the breakdown voltages of 165 and 90 V, respectively.

High Performance Low-Voltage Power MOSFETs with Hybrid Waffle Layout Structure in a 0.25μ Standard CMOS Process

This paper reports on a low-voltage CMOS power MOSFET layout technique, implemented in a 0.25 mum, 5-metal layers CMOS process that is suitable for high speed switching power devices. The proposed hybrid waffle (HW) layout technique organizes MOSFET fingers in a square grid (waffle) arrangement. It is designed to provide an effective trade-off between the width of diagonal source/drain metal and the active device area, allowing more effective optimization between switching and conduction losses. In comparison with conventional multi-finger (MF) layouts, the HW layout is found to exhibit a 30% reduction in overall on-resistance with 3.6 times smaller total gate charge for CMOS devices with a current rating of 1 A. Integrated DC-DC buck converters using HW push-pull output stages are found to have higher simulated power conversion efficiencies at switching frequencies beyond multi-MHz.

High performance CMOS-compatible super-junction FINFETs for Sub-100V applications

A novel lateral super-junction power FINFET (SJ-FINFET) structure suitable for integration is presented to address the challenges associated with sub-100V applications. The proposed lateral SJ-FINFET structure is compatible with advanced SOI-CMOS and FINFET fabrication technologies. It employs a 3D corrugated MOS channel and alternating n/p drift region pillars to achieve a 30% reduction in specific on-resistance when compared to conventional planar gate SJ-LDMOSFETs.

High speed CMOS output stage for integrated DC-DC converters

A Hybrid Waffle layout technique is introduced for the design of CMOS power transistors in integrated low voltage DC-DC converters. Comparing with conventional multi-finger layout scheme, the Hybrid Waffle layout scheme allows optimized trade-off between device on-resistance and metal interconnect resistance to minimize overall on-resistance. Interestingly, the reduced channel width per unit area also leads to lower gate capacitance and faster switching speed. This paper presents a prototype DC-DC converter IC that contains integrated gate drivers, protection circuits and CMOS output transistors. Implemented in a standard 0.25 ¿m CMOS, this IC can be switched at 12.5 MHz with output current rated at 800 mA with input voltage of up to 4.2 V. Peak power efficiency of 85% was observed at 100 mA. Die size is 1.1 × 1.5 mm2.

A Floating RESURF EDMOS with Enhanced Ruggedness and Safe Operating Area

In this paper, a floating RESURF EDMOS (BV = 55 V, Ron,sp = 36.5 mOmegamiddotmm2) with 45% increased ruggedness and 400% enhanced safe operating area (SOA) is discussed and compared to the conventional EDMOS structure. The proposed EDMOS has both drain and source engineering to enhance device ruggedness, not only via reducing the base resistance of the parasitic bipolar transistor, but also suppressing the base current of the parasitic bipolar transistor at high VGS and high VDS situations, which will also improve the device SOA. Furthermore, the buried deep Nwell allow the device to have better tradeoff between breakdown voltage and on-resistance.

FOM (Figure of Merit) Analysis for Low Voltage Power MOSFETs in DC-DC Converter

FOM is a generally accepted performance and efficiency indicator for power MOSFETs. However, it is found that the traditional FOM can no longer provide a quick measure of the overall device performance for switched mode power supplies, especially for DC-DC converters using the low voltage (sub-lOV) power MOSFETs fabricated in a deep sub-micron CMOS technology. To give a subjective analysis, a new comparison method has been proposed to compare the true overall device performance and power conversion efficiency.

Advanced lateral power MOSFETs for power integrated circuits

CMOS compatible power devices have been an intensely pursued area in the past few decades. Power integrated circuit technologies are now accessible by many designers via popular foundry services. This paper is a brief review on modern integrated power transistors including the recently introduced CMOS compatible Orthogonal Gate extended drain MOSFETs (OG-EDMOS) and the lateral superjunction power FINFETs with embedded 3D trench gate. The characteristics of these devices are discussed and a perspective on the future trend of integrated power transistors is presented.

A floating RESURF EDMOS with enhanced safe operating area

In this paper, a floating RESURF EDMOS (BV=55V, Ron,sp=36.5mOmega-mm2) with 400% enhanced Safe Operating Area (SOA) will be discussed and compared to the conventional EDMOS structure. The proposed EDMOS has both drain and source engineering to enhance SOA, not only via reducing the base resistance of the parasitic bipolar transistor, but also suppressing the base current of the parasitic bipolar transistor at high VGs and high VDs situations. Furthermore, the buried deep Nwell allow the device to have better tradeoff between breakdown voltage and on-resistance.