Achim Trautmann

Eutectic wafer bonding for 3-D integration

Successful commercialization of MEMS products extremely depends on cost factors. Especially the role of integration technologies like packaging at different levels, combining MEMS with integrated circuits, and to realize 3-dimensional packaged devices is more important than ever. Bonding technologies at wafer level are key factors for 3-d integration, realizing the mechanical bond and fulfilling certain requirements like strength, hermeticity, and reliability as well as the electrical interconnection of the different functional components. From a great variety of bonding techniques eutectic bonding has got a special importance today because both hermetically sealed packages and electrical interconnects could be performed within one bonding process. Furthermore, there are some advantages such as low processing temperature, low resulting stress, and high bonding strength. These properties are mainly investigated up today. Since the early 90-ies eutectic wafer bonding is known from very large scale integration (VLSI) and is used very often in industry. Even before that time eutectic bond processes were already used in the field of chip bonding. Within this paper the development and investigation of at least two eutectic bonding technologies will be described and characterized. Although the mechanical and micro structural properties of the bond will be shown, the realization and test of electrical interconnects is focused very clearly. With an integration of certain test structures the bonding strength, the electrical properties, and the hermeticity of eutectic bonds could be measured and evaluated. At least it will be concluded with an outlook for the feasibility of eutectic bonding in 3-d integrated smart micro systems.

Characterization of Diverse Gate Oxides on 4H-SiC 3D Trench-MOS Structures

This study focuses on the characterization of silicon dioxide (SiO2) layers, either thermally grown or deposited on trenched 100 mm 4H-silicon carbide (SiC) wafers. We evaluate the electrical properties of silicon dioxide as a gate oxide (GOX) for 3D metal oxide semiconductor (MOS) devices, such as Trench-MOSFETs. Interface state densities (DIT) of 1*1011 cm-2 eV-1 under flat band conditions were determined using the hi-lo CV-method [1]. Furthermore, current-electric field strength (IE) measurements have been performed and are discussed. Trench-MOS structures exhibited dielectric breakdown field strengths up to 10 MV/cm.

Investigation of Trenched and High Temperature Annealed 4H-SiC

This study focuses on the effects of a high temperature anneal after dry etching of trenches (post-trench anneal, PTA) on 4Hsilicon carbide (4H-SiC). We aim at the optimum 4H-SiC post-trench treatment with respect to the fabrication and the operation of a trenched gate metal oxide semiconductor field effect transistor (Trench-MOSFET). PTA significantly reduces micro-trenches, also called sub-trenches [, in the corners of the bottom of the trench. This is highly beneficial in case the etched trench sidewall is used as the channel of a Trench-MOSFET. However, PTA is also shown to cause a slight enlargement of the trench width along with a considerable increase of the substrate surface roughness. In addition, X-ray photoelectron spectroscopy (XPS) depth profiles indicate an increased carbon atom concentration at the 4H-SiC surface after the high temperature PTA. The non-stoichiometric surface composition affects the quasi-static capacitance-voltage (QSCV) behavior of MOS structures using a deposited gate oxide (GOX). We assume that a sacrificial oxidation directly after the PTA could restore a stoichiometric 4H-SiC surface.

Influence of Diverse Post-Trench Processes on the Electrical Performance of 4H-SiC MOS Structures

This paper focuses on the evaluation of subsequent process steps (post-trench processes, PTPs) after 4H silicon carbide (4H-SiC) trench etching with respect to the electrical performance of trenched gate metal oxide semiconductor field effect transistors (Trench-MOSFETs). Two different types of PTP were applied after 4H-SiC trench formation, a high temperature post-trench anneal (PTA) [1] and a sacrificial oxidation (SacOx) [2]. We found significantly improved electrical properties of Planar-MOS structures using a SacOx as PTP, prior to gate oxide deposition. Besides excellent quasi-static capacitance-voltage (QSCV) behavior even at T = 250 °C, charge-to-breakdown (QBD) results up to 8.8 C/cm2 at T = 200 °C are shown to be similar on trenched surfaces as well as on untrenched surfaces of SacOx-treated Planar-MOS structures. Moreover, dielectric breakdown field strengths up to 12 MV/cm have been measured on Planar-MOS structures. However, thick bottom oxide Trench-MOS structures indicate best dielectric breakdown field strengths of 9.5 MV/cm when using a trench shape rounding PTA as the PTP.