Ada Wille

First polarization-engineered compressively strained AlInGaN barrier enhancement-mode MISHFET

One current focus of research is the realization of GaN-based enhancement-mode devices. A novel approach for the realization of enhancement-mode behaviour is the utilization of polarization matching between the barrier and the GaN buffer. Yet, the utilization of a quaternary barrier combining polarization engineering together with a large conduction band offset has not been demonstrated so far. Here, epitaxially grown, compressively strained AlInGaN is applied as a nearly polarization-matched barrier layer on GaN resulting in enhancement-mode operation. The insulated-gate devices are fabricated gate-first with Al2O3 as gate dielectric. Passivated metal insulator semiconductor heterostructure field effect transistors yielded threshold voltages (Vth) of up to +1 V. The devices withstand negative and positive gate-biased stress and a positive Vth is maintained even after long-time negative bias stress.

Relaxation and critical strain for maximum In incorporation in AlInGaN on GaN grown by metal organic vapour phase epitaxy

Quaternary AlInGaN layers were grown on conventional GaN buffer layers on sapphire by metal organic vapour phase epitaxy at different surface temperatures and different reactor pressures with constant precursor flow conditions. A wide range in compositions within 30–62% Al, 5–29% In, and 23–53% Ga was covered, which leads to different strain states from high tensile to high compressive. From high-resolution x-ray diffraction and Rutherford backscattering spectrometry, we determined the compositions, strain states, and crystal quality of the AlInGaN layers. Atomic force microscopy measurements were performed to characterize the surface morphology. A critical strain value for maximum In incorporation near the AlInGaN/GaN interface is presented. For compressively strained layers, In incorporation is limited at the interface as residual strain cannot exceed an empirical critical value of about 1.1%. Relaxation occurs at about 15 nm thickness accompanied by strong In pulling. Tensile strained layers can be gro...

Effect of stress voltage on the dynamic buffer response of GaN-on-silicon transistors

Back-gated measurements on conductive silicon substrates have been performed to investigate the effect of stress voltage on the dynamic behaviour of GaN-on-silicon (GaN-on-Si) transistors. Two comparable samples were studied with the only difference being the vertical dislocation density. Results show a clear correlation between dislocation density and the ability of the GaN buffer to dynamically discharge under high stress conditions.

Pseudo-vertical GaN-based trench gate metal oxide semiconductor field effect transistor

We report on the fabrication and characterisation of an enhancement mode n-channel pseudo-vertical GaN metal oxide semiconductor field effect transistor (MOSFET), which utilizes a high-k dielectric covered trench gate and a top side drain contact. The processing technology has been developed to be easily transferrable to a truly vertical MOSFET on GaN bulk material, as targeted for high-voltage power switching applications. Device functionality is demonstrated by linear transfer characteristic with a decent ON/OFF current ratio of 6 orders of magnitude and clear normally-off operation.