Farzan Jazaeri

Modeling and Design Space of Junctionless Symmetric DG MOSFETs With Long Channel

In this paper, we investigate the technological constrains and design limitations of ultrathin body junctionless double gate MOSFET (JL DG MOSFET). Relationships between the silicon thickness and the doping concentration compatible with design requirements in terms of OFF-state-current and voltages are obtained and validated with TCAD simulations. This set of analytical expressions can be used as a guideline for technology optimization of JL DG MOSFETs.

A Common Core Model for Junctionless Nanowires and Symmetric Double-Gate FETs

In this paper, we evidence the link between the planar and cylindrical junctionless field effect transistors (JL-FETs) from the electrostatics and current point of view. In particular, we show that an approximate solution of the Poisson-Boltzmann equation for JL nanowires can be mapped on the planar double-gate topology generating only negligible mismatch, meaning that both devices can share the same core model as far as long channels are considered. These preliminary results are a first step toward a unification of compact models for JL-FETs.

Trans-Capacitance Modeling in Junctionless Symmetric Double-Gate MOSFETs

We have developed a closed-form solution for trans-capacitances in long-channel junctionless double-gate (JL DG) MOSFET. This approach, which is derived from a coherent charge-based model, was fully validated with technology computer-aided design simulations. According to this paper, a complete intrinsic capacitance network is obtained, which represents an essential step toward ac analysis of circuits based on junctionless devices.

Modeling Asymmetric Operation in Double-Gate Junctionless FETs by Means of Symmetric Devices

This paper aims to model asymmetric operation in double-gate junctionless FETs. Following a rigorous approach, we find that asymmetric operation can be simulated by combining two symmetric junctionless FETs, what we call the virtual symmetric device concept. In addition to the benefits in terms of compactness and coherence, such equivalence is used to develop a complete charge-based model for independent double-gate junctionless architectures, including mismatch in gate capacitance and material work functions.

Generalized Charge-Based Model of Double-Gate Junctionless FETs, Including Inversion

In this brief, we have developed a charge-based model for the symmetric double-gate junctionless (JL) field effect transistor (FET) that also accounts for the inversion layer when the gate voltage is biased in deep depletion. Basically, this approach represents a generalization of a former model and aims at giving a unified description of JL FETs beyond the domain of operation for which they have been designed. In addition, to its interest for providing technology design rules, the new model is able to explain the unexpected increase in the gate capacitance when biasing the device in deep depletion as well as the theoretical limit for the OFF-current in deep depletion.

Impact of GigaRad Ionizing Dose on 28 nm bulk MOSFETs for future HL-LHC

The Large Hadron Collider (LHC) running at CERN will soon be upgraded to increase its luminosity giving rise to radiations reaching the level of GigaRad Total Ionizing Dose (TID). This paper investigates the impact of such high radiation on transistors fabricated in a commercial 28 nm bulk CMOS process with the perspective of using it for the future silicon-based detectors. The DC electrical behavior of nMOSFETs is studied up to 1 Grad TID. All tested devices demonstrate to withstand that dose without any radiation-hard layout techniques. In spite of that, they experience a significant drain leakage current increase which may affect normal device operation. In addition, a moderate threshold voltage shift and subthreshold slope degradation is observed. These phenomena have been linked to radiation-induced effects like interface and switching oxide traps, together with parasitic side-wall transistors.

Charge-Based Modeling of Double-Gate and Nanowire Junctionless FETs Including Interface-Trapped Charges

Nanowire (NW) semiconductors are interesting devices for being used as sensors. Such NWs are doped silicon channels with electrical contacts at both ends, which is a kind of the so-called junctionless (JL) device. However, in contrast with the state-of-the-art CMOS FETs, a relatively high concentration of traps is expected when using these architectures as biosensors, since their surface is supposed to be in contact with chemicals and gases. A major concern is that these traps will substantially modify the charge-voltage characteristics, thus asking for improvement of basic compact models. In this respect, we have included the effect of interface traps in NW and double-gate JL devices through a charge-based model that has been developed previously. The soundness of this approach is confirmed by extensive comparisons with numerical technology computer-aided design simulation, while the analytical formulation helps understanding the most relevant parameters of the traps with respect to the technology.

GigaRad total ionizing dose and post-irradiation effects on 28 nm bulk MOSFETs

The DC performance of both n- and pMOSFETs fabricated in a commercial-grade 28 nm bulk CMOS process has been studied up to 1 Grad of total ionizing dose and at post-irradiation annealing. The aim is to assess the potential use of such an advanced CMOS technology in the forthcoming upgrade of the Large Hadron Collider at CERN. The total ionizing dose effects show limited influence in the drive current of all the tested nMOSFETs. Nonetheless, the leakage current increases significantly, affecting the normal device operation of the nMOSFETs. These phenomena can be linked to the charge trapping in the oxides and at the Si/oxide interfaces, related to both the gate oxide and the shallow trench isolation oxide. In addition, it has been observed that the radiation-induced effects are partly recovered by the long-term post-irradiation annealing. To quantify the total ionizing dose effects on DC characteristics, the threshold voltage, subthreshold swing, and drain induced barrier lowering have also been extracted for nMOSFETs.

Mobility Measurement in Nanowires Based on Magnetic Field-Induced Current Splitting Method in H-Shape Devices

This paper investigates a new method to measure mobility in nanowires. With a simple analytical approach and numerical simulations, we bring evidence that the traditional technique of Hall voltage measurement in low-dimensional structures such as nanowires may generate large errors, while being challenging from a technological aspect. Here, we propose to extract the drift mobility in nanowires by measuring a variation of the electric current caused by the presence of a magnetic field, in a specific nanowire network topology. This method overcomes the limitations inherent to the standard Hall effect technique and might open the way to a more precise and simple measurement of mobility in nanowires, still a matter for intensive research.

Modeling Channel Thermal Noise and Induced Gate Noise in Junctionless FETs

This paper presents analytical expressions for channel noise, induced gate noise (IGN), and cross-correlation noise in a long-channel junctionless (JL) double-gate MOSFET. The analytical relationships, which have been derived from a coherent charge-based model, are validated with technology computer-aided design simulations, and the figures of merit have been compared with the inversion mode FETs. For a given current, we found that the channel thermal noise is very similar for both architectures, whereas the IGN is slightly decreased in the JL FETs.