Adithyaram Narasimha

A Grating-Coupler-Enabled CMOS Photonics Platform

We have developed a silicon photonics platform that allows monolithic integration with electronic circuits in a CMOS-compatible process. In this platform, vertical couplers are found to be a superior solution compared to traditional edge-coupling techniques. Grating couplers are an essential element in developing the optical wafer-scale test infrastructure, which in turn, enables the development of the photonic device library. The photonic devices were assembled into a 4 × 10 Gb/s transceiver die that also contains modulator drive, control, and receive electronics.

A Fully Integrated 20-Gb/s Optoelectronic Transceiver Implemented in a Standard 0.13-

A dual-channel 10 Gb/s per channel single-chip optoelectronic transceiver has been demonstrated in a 0.13-mum CMOS SOI technology. The transceiver integrates conventionally discrete optoelectronic functions such as high-speed 10-Gb/s electro-optic modulation and 10-Gb/s optical reception on an SOI substrate using a standard CMOS process. The high optical index contrast between silicon (n=3.5) and its oxide (n=1.5) allows for very large scale integration of optical devices, while the use of a standard CMOS process allows these devices to be seamlessly fabricated together with electronics on the same substrate. Such a high level of optoelectronic integration is unprecedented, and serves to substantially reduce system footprint and power dissipation, allowing efficient scaling to higher data rates and broader functionality. This paper describes the photonic components, electronic blocks, and architecture of a CMOS photonic transceiver that achieves an aggregate data rate of 20Gb/s in a dual-channel package, with a BER of less than 10-15 and a power consumption of 1.25 W per channel with both channels operating simultaneously

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We demonstrate monolithically integrated 4×10 Gb/s WDM transceivers built in a production 130 nm SOI CMOS process. Only light sources are external to the chip. 40 Gb/s error-free, bidirectional transmission is demonstrated.

CMOS SOI Technology

Optical and electronic building blocks required for DWDM transceivers have been integrated in a 0.13 mum CMOS SOI technology. Using these building blocks, a 4 x 10-Gb/s single-chip DWDM optoelectronic transceiver with 200 GHz channel spacing has been demonstrated. The DWDM transceiver demonstrates an unprecedented level of optoelectronic system integration, bringing all required optical and electronic transceiver functions together on a single SOI substrate. An aggregate data rate of 40 Gb/s was achieved over a single fiber, with a BER of less than 10-12 and a power consumption of 3.5 W.

Monolithically integrated high-speed CMOS photonic transceivers

We have demonstrated a CMOS Optoelectronic technology platform, using a 650mW 4×10-Gb/s 0.13 μm silicon-on-insulator integrated transceiver chip, co-packaged with an externally modulated laser, to enable high density data interconnects at <

A Fully Integrated 4

1 per Gbps.

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We have demonstrated a 40-Gb/s optoelectronic transceiver in a quad small form-factor pluggable (QSFP) module. Each module includes a 4xlO-Gb/s, 0.13 μm CMOS silicon-on-insulator integrated optoelectronic transceiver chip co-packaged with a single, externally modulated CW laser.

10-Gb/s DWDM Optoelectronic Transceiver Implemented in a Standard 0.13

We present our approach to a low-cost, highly scalable opto-electronic integration platform based on a commercial CMOS process. In this talk, we detail the performance of the device library elements and highlight performance trade-offs encountered in monolithically integrating optical and electronic circuits. We describe an opto-electronic integrated circuit (OEIC) design toolkit modeled after the standard electronic design flow, which includes automated design rule checking (DRC) and layout-versus-schematic (LVS) checks covering all types of circuit elements. As an example of integration, we detail the design of a multi-channel transceiver chip with 10 Gbps/channel optical data transmission speed and report on its performance.

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The advantages of CMOS photonics for next generation transceiver applications are outlined in terms of raw bandwidth, channel capacity, reach, power, cost, link performance and reliability. The advantages for future integration with host chips area also discussed.

CMOS SOI Technology

For the first time we demonstrate a fully self-contained photonic transceiver system on a single die with monolithically integrated Ge photo-detectors. The transceiver allows error-free bidirectional 4times10 Gb/s WDM transmission using a single CMOS die at each end of the link.