Drew Guckenberger

A Fully Integrated 20-Gb/s Optoelectronic Transceiver Implemented in a Standard 0.13-

A dual-channel 10 Gb/s per channel single-chip optoelectronic transceiver has been demonstrated in a 0.13-mum CMOS SOI technology. The transceiver integrates conventionally discrete optoelectronic functions such as high-speed 10-Gb/s electro-optic modulation and 10-Gb/s optical reception on an SOI substrate using a standard CMOS process. The high optical index contrast between silicon (n=3.5) and its oxide (n=1.5) allows for very large scale integration of optical devices, while the use of a standard CMOS process allows these devices to be seamlessly fabricated together with electronics on the same substrate. Such a high level of optoelectronic integration is unprecedented, and serves to substantially reduce system footprint and power dissipation, allowing efficient scaling to higher data rates and broader functionality. This paper describes the photonic components, electronic blocks, and architecture of a CMOS photonic transceiver that achieves an aggregate data rate of 20Gb/s in a dual-channel package, with a BER of less than 10-15 and a power consumption of 1.25 W per channel with both channels operating simultaneously

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We demonstrate monolithically integrated 4×10 Gb/s WDM transceivers built in a production 130 nm SOI CMOS process. Only light sources are external to the chip. 40 Gb/s error-free, bidirectional transmission is demonstrated.

CMOS SOI Technology

We have demonstrated a CMOS Optoelectronic technology platform, using a 650mW 4×10-Gb/s 0.13 μm silicon-on-insulator integrated transceiver chip, co-packaged with an externally modulated laser, to enable high density data interconnects at <

Monolithically integrated high-speed CMOS photonic transceivers

1 per Gbps.

An ultra low power CMOS photonics technology platform for H/S optoelectronic transceivers at less than

We have demonstrated a 40-Gb/s optoelectronic transceiver in a quad small form-factor pluggable (QSFP) module. Each module includes a 4xlO-Gb/s, 0.13 μm CMOS silicon-on-insulator integrated optoelectronic transceiver chip co-packaged with a single, externally modulated CW laser.

1 per Gbps

The advantages of CMOS photonics for next generation transceiver applications are outlined in terms of raw bandwidth, channel capacity, reach, power, cost, link performance and reliability. The advantages for future integration with host chips area also discussed.

A 40-Gb/s QSFP Optoelectronic Transceiver in a 0.13μm CMOS Silicon-on-Insulator Technology

For the first time we demonstrate a fully self-contained photonic transceiver system on a single die with monolithically integrated Ge photo-detectors. The transceiver allows error-free bidirectional 4times10 Gb/s WDM transmission using a single CMOS die at each end of the link.

Advantages of CMOS photonics for future transceiver applications

A mostly integrated 10.2GHz optoelectronic oscillator (OEO) using Si photonics monolithic integration technology is reported. The OEO is a chip-scale device manufactured using a standard 0.13mum SOI CMOS process, with phase noise of -112dBc/Hz at 10kHz carrier offset and RF power consumption of less than 800mW.

Demonstration of first WDM CMOS photonics transceiver with monolithically integrated photo-detectors

Silicon-based CMOS Photonics offers many advantages when implementing microwave photonic systems. The toolset available in CMOS photonics and the advantages it offers for the implementation of microwave photonic systems are presented here.

A Low Phase Noise 10GHz Optoelectronic RF Oscillator Implemented Using CMOS Photonics

A library of photonic components integrated in a silicon CMOS technology is presented as an enabling technology platform for radio-over-fiber systems, allowing increased levels of integration to be achieved, and thereby reducing size and cost.