Ahmad Mirzaei

The Quadrature LC Oscillator: A Complete Portrait Based on Injection Locking

We show that the quadrature LC oscillator is best treated as two strongly coupled, nominally identical oscillators that are locked to the same frequency. Differential equations that extend Adlers description of locking to strong injection reveal the full dynamics of this circuit. With a simplifying insight, the analysis reveals all the modes of the oscillator, their stability, the effects of mismatch on quadrature phase accuracy, and through a novel use of the analysis, phase noise.

A Blocker-Tolerant, Noise-Cancelling Receiver Suitable for Wideband Wireless Applications

A new wideband receiver architecture is proposed that employs two separate passive-mixer-based downconversion paths, which enables noise cancelling, but avoids voltage gain at blocker frequencies. This approach significantly relaxes the trade-off between noise, out-of-band linearity and wideband operation. The resulting prototype in 40 nm is functional from 80 MHz to 2.7 GHz and achieves a 2 dB noise figure, which only degrades to 4.1 dB in the presence of a 0 dBm blocker.

Analysis and Optimization of Direct-Conversion Receivers With 25% Duty-Cycle Current-Driven Passive Mixers

The performance of zero-IF receivers with current-driven passive mixers driven by 25% duty-cycle quadrature clocks is studied and analyzed. It is shown that, in general, these receivers outperform the ones that utilize passive mixers with 50% duty-cycle clocks. The known problems in receivers with 50% duty-cycle mixers, such as having unequal high- and low-side conversion gains, unexpected IIP2 and IIP3 numbers, and IQ crosstalk, are significantly lowered due to the operating principles of the 25% duty-cycle passive mixer. It is revealed that with an intelligent sizing of the design parameters, the 25%-duty-cycle-mixer-based receiver is superior in terms of linearity, noise, and elimination of IQ crosstalk.

Analysis and Optimization of Current-Driven Passive Mixers in Narrowband Direct-Conversion Receivers

Properties of the current-driven passive mixer are explored to maximize its performance in a zero-IF receiver. Since there is no reverse isolation between the RF and baseband sides of the mixer, the mixer reflects the baseband impedance to the RF and vice versa through simple frequency shifting. It is also shown that in an IQ down-conversion system the lack of reverse isolation causes a mutual interaction between the two quadrature mixers, which results in different high- and low-side conversion gains, and unexpected IIP2 and IIP3 values. With a thorough and accurate mathematical analysis it is shown how to design this mixer and its current buffer, and how to size components to get the best linearity, conversion gain and noise figure while alleviating the IQ cross-talk problem.

A 65 nm CMOS Quad-Band SAW-Less Receiver SoC for GSM/GPRS/EDGE

A quad-band 2.5G receiver is designed to replace the front-end SAW filters with on-chip bandpass filters and to integrate the LNA matching components, as well as the RF baluns. The receiver achieves a typical sensitivity of -110 dBm or better, while saving a considerable amount of BOM. Utilizing an arrangement of four baseband capacitors and MOS switches driven by 4-phase 25% duty-cycle clocks, high-Q BPFs are realized to attenuate the 0 dBm out-of-band blocker. The 65 nm CMOS SAW-less receiver integrated as a part of a 2.5G SoC, draws 55 mA from the battery, and measures an out-of-band 1 dB-compression of greater than +2 dBm. Measured as a stand-alone, as well as the baseband running in call mode in the platform level, the receiver passes the 3GPP specifications with margin.

Multi-Phase Injection Widens Lock Range of Ring-Oscillator-Based Frequency Dividers

Injection-locked oscillators divide at very high frequencies and consume low power. They are not widely deployed in commercial products because they operate over small, often unpredictable, ranges of input frequencies. Ring oscillators as dividers are interesting because they are compact, and capable of a multi-phase output, including quadrature phases. Using a generalized Adlers equation for large injections, we analyze the operation of injection-locked ring oscillators and derive expressions for the input lock range. We discover that injection in the correct progressive phases greatly widens the lock range; all that is needed is the right delay cell circuit, and the injection input in one or two phases. As proof of concept, divide-by-two and six prototypes are built. The measured lock range spans DC to 1.5 the free-running frequency, the highest reported to date.

A blocker-tolerant wideband noise-cancelling receiver with a 2dB noise figure

As narrowband off-chip RF filtering is not compatible with the concept of software-defined radio (SDR), an SDR receiver must be designed to tolerate large out-of-band blockers with minimal gain compression and noise figure degradation. A recent circuit tackles this problem by dispensing with the LNA entirely. This mixer-first approach achieves impressive linearity, but at the expense of noise figure and, since such a receiver has no gain prior to down-conversion, the flicker noise corner can be unacceptably high. Other SDR attempts invariably use a noise-cancelling LNA at the front end, which provides wideband matching, however such approaches have either inadequate linearity or display too large a noise for our purposes. In this work, we propose a hybrid frequency-translational, noise-cancelling (FTNC) receiver that employs two separate down-conversion paths to enable noise cancelling with no voltage gain prior to base-band filtering. The resulting design has a sub-2dB noise figure and tolerates 0dBm blockers with no gain back-off, breaking the traditional noise-linearity trade-off common in all receivers.

Architectural Evolution of Integrated M-Phase High-Q Bandpass Filters

-phase bandpass filters (BPFs) are analyzed, and variations of the structure are proposed. For values of that are integer multiples of 4, the conventional -phase BPF structure is modified to take complex baseband impedances and frequency-translate their complex impedance response to the local oscillator frequency. Also, it is demonstrated how the -phase BPF can be modified to implement a high quality factor (Q) image-rejection BPF with quadrature RF inputs. In addition, we present high-Q BPFs whose center frequencies are equal to the sum or difference of the RF and IF (intermediate frequency) clocks. Such filters can be useful in heterodyne receiver architectures.

Analysis of Imperfections on Performance of 4-Phase Passive-Mixer-Based High-Q Bandpass Filters in SAW-Less Receivers

It has been shown that an arrangement of four MOS switches and four baseband lowpass impedances can synthesize on-chip high-Q bandpass filters if the switches are driven by proper clock phases. The technique has been successfully utilized in receivers to replace external SAW filters. This paper analyzes performance of these filters in SAW-less receivers against imperfections such as clock phase-noise, thermal noise of switches, second-order non-linearity of switches and clock phase error. Such receivers deal with out-of-band blockers by utilizing on-chip high-Q 4-phase bandpass filters.

A Low-Power Process-Scalable Super-Heterodyne Receiver With Integrated High-

A super-heterodyne receiver utilizing integrated high-Q filters to condition the desired signal to be digitized by a bandpass ADC at an IF of 110 MHz achieves a NF of 2.8 dB and an IIP3 of -8.4 dBm. The conventional M-phase filter is developed to a new form of high-Q filter that is centered at sum or difference of two clocks. The M-phase filter is also evolved to take two quadrature inputs to perform image rejection, while exhibiting a high-Q bandpass response with desired signal located in the center. Built of inverters, switches, and MOS capacitors, the receiver follows technology scaling and is reconfigurable through a clock. The receiver including the dividers and LO path draws 12 mA of battery current and occupies 0.76 mm2 in 65-nm CMOS.