Mohammad E. Heidari

An 800-MHz–6-GHz Software-Defined Wireless Receiver in 90-nm CMOS

A software-defined radio receiver is designed from a low-power ADC perspective, exploiting programmability of windowed integration sampler and clock-programmable discrete-time analog filters. To cover the major frequency bands in use today, a wideband RF front-end, including the low-noise amplifier (LNA) and a wide tuning-range synthesizer, spanning over 800 MHz to 6 GHz is designed. The wideband LNA provides 18-20 dB of maximum gain and 3-3.5 dB of noise figure over 800 MHz to 6 GHz. A low 1/f noise and high-linearity mixer is designed which utilizes the passive mixer core properties and provides around +70 dBm IIP2 over the bandwidth of operation. The entire receiver circuits are implemented in 90-nm CMOS technology. Programmability of the receiver is tested for GSM and 802.11g standards

The Quadrature LC Oscillator: A Complete Portrait Based on Injection Locking

We show that the quadrature LC oscillator is best treated as two strongly coupled, nominally identical oscillators that are locked to the same frequency. Differential equations that extend Adlers description of locking to strong injection reveal the full dynamics of this circuit. With a simplifying insight, the analysis reveals all the modes of the oscillator, their stability, the effects of mismatch on quadrature phase accuracy, and through a novel use of the analysis, phase noise.

An 800MHz to 5GHz Software-Defined Radio Receiver in 90nm CMOS

A 90nm CMOS RX operates over the 800MHz to 5GHz band uses a passive FET mixer driven by a capacitively coupled RF transconductor, and a combination of CT and DT analog FIR and MR filters to achieve >100dB of programmable anti-aliasing. The RX chain has 5 to 5.5dB NF, -3.5dBm IIP3, 39dBm IIP2, 10 to 66dB of gain, and draws 11.4mA from 2.5V and 8 to 28mA (depending on RX mode) from 1V

Software-defined radio receiver: dream to reality

This article describes a fully integrated 90 nm CMOS software-defined radio receiver operating in the 800 MHz to 5 GHz band. Unlike the classical SDR paradigm, which digitizes the whole spectrum uniformly, this receiver acts as a signal conditioner for the analog-to-digital converters, emphasizing only the wanted channel. Thus, the ADCs operate with modest resolution and sample rate, consuming low power. This approach makes portable SDR a reality

Multi-Phase Injection Widens Lock Range of Ring-Oscillator-Based Frequency Dividers

Injection-locked oscillators divide at very high frequencies and consume low power. They are not widely deployed in commercial products because they operate over small, often unpredictable, ranges of input frequencies. Ring oscillators as dividers are interesting because they are compact, and capable of a multi-phase output, including quadrature phases. Using a generalized Adlers equation for large injections, we analyze the operation of injection-locked ring oscillators and derive expressions for the input lock range. We discover that injection in the correct progressive phases greatly widens the lock range; all that is needed is the right delay cell circuit, and the injection input in one or two phases. As proof of concept, divide-by-two and six prototypes are built. The measured lock range spans DC to 1.5 the free-running frequency, the highest reported to date.

A low noise, wideband digital phase-locked loop based on a new time-to-digital converter with subpicosecond resolution

A digital PLL uses a high resolution coarse-fine time-to-digital converter (TDC) for wide loop bandwidth. The loop bandwidth is set to 400 kHz with a 26 MHz reference for GSM. The in-band phase noise contribution from the TDC is -116 dBc/Hz, the phase noise is -117 dBc/Hz at high-band 400 kHz offset, and the RMS phase error is 0.3deg.

All-Digital Outphasing Modulator for a Software-Defined Transmitter

An all-digital outphasing modulator to be used in a software-defined radio (SDR) transmitter is presented. A digitally-controlled oscillator (DCO) followed by two digital phase rotators (DPR) are the main building blocks. The DCO and DPRs are enclosed, respectively, by a phase-locked loop and two delay-locked loop. All functions, including filtering and calibration are performed in a digital signal processor (DSP). The chip was fabricated in a 90 nm CMOS process and tested for GSM and WCDMA. The total active area of the chip is 3 mm2 . Semi-analog blocks (DCO core, DPR core and their buffers) and digital processor consume 30 mA and 25 mA, respectively. Current consumption of the phase-to-digital converter is 70 mA, which can be reduced to 30% by gating off the circuit during idle times.

Analysis of Oscillators Locked by Large Injection Signals: Generalized Adler's Equation and Geometrical Interpretation

Using the hard-limiting characteristics of transconductors, a new model for injection-locking, applicable for any strong and weak injection, is proposed. Backed by simulations, examples of the powerfulness of this new model are enumerated as proof of the concept.

All-digital out-phasing modulator for a software-defined transmitter

An all-digital out-phasing transmitter suitable for software-defined radio (SDR) is presented. It uses a phase-locked loop followed by two digital phase rotator blocks embedded in two delay-locked loops. The chip is fabricated in a 90 nm CMOS process with total active area of 3 mm2, and tested for GSM and WCDMA standards. The whole transmitter excluding phase-to-digital converter (PDC) consumes 55 mA, and current consumption of the PDC is 70 mA.

Injection-Locked Frequency Dividers based on Ring Oscillators with Optimum Injection for Wide Lock Range

Divide-by-2 and divide-by-6 ring oscillators use multi-phase injection to operate from near DC to 1.7 and 1.2 GHz input frequencies, respectively. In 0.13-mum CMOS, the circuits consume 0.25 mA per stage