Saeed Chehrazi

An 800-MHz–6-GHz Software-Defined Wireless Receiver in 90-nm CMOS

A software-defined radio receiver is designed from a low-power ADC perspective, exploiting programmability of windowed integration sampler and clock-programmable discrete-time analog filters. To cover the major frequency bands in use today, a wideband RF front-end, including the low-noise amplifier (LNA) and a wide tuning-range synthesizer, spanning over 800 MHz to 6 GHz is designed. The wideband LNA provides 18-20 dB of maximum gain and 3-3.5 dB of noise figure over 800 MHz to 6 GHz. A low 1/f noise and high-linearity mixer is designed which utilizes the passive mixer core properties and provides around +70 dBm IIP2 over the bandwidth of operation. The entire receiver circuits are implemented in 90-nm CMOS technology. Programmability of the receiver is tested for GSM and 802.11g standards

The Quadrature LC Oscillator: A Complete Portrait Based on Injection Locking

We show that the quadrature LC oscillator is best treated as two strongly coupled, nominally identical oscillators that are locked to the same frequency. Differential equations that extend Adlers description of locking to strong injection reveal the full dynamics of this circuit. With a simplifying insight, the analysis reveals all the modes of the oscillator, their stability, the effects of mismatch on quadrature phase accuracy, and through a novel use of the analysis, phase noise.

An 800MHz to 5GHz Software-Defined Radio Receiver in 90nm CMOS

A 90nm CMOS RX operates over the 800MHz to 5GHz band uses a passive FET mixer driven by a capacitively coupled RF transconductor, and a combination of CT and DT analog FIR and MR filters to achieve >100dB of programmable anti-aliasing. The RX chain has 5 to 5.5dB NF, -3.5dBm IIP3, 39dBm IIP2, 10 to 66dB of gain, and draws 11.4mA from 2.5V and 8 to 28mA (depending on RX mode) from 1V

A 6.5 GHz wideband CMOS low noise amplifier for multi-band use

LNA based on a noise-cancelled common gate topology spans 0.1 to 6.5 GHz with a gain of 19 dB, a NF of 3 dB, and s11 < -10 dB. It is realized in 0.13-mum CMOS and dissipates 12 mW

Software-defined radio receiver: dream to reality

This article describes a fully integrated 90 nm CMOS software-defined radio receiver operating in the 800 MHz to 5 GHz band. Unlike the classical SDR paradigm, which digitizes the whole spectrum uniformly, this receiver acts as a signal conditioner for the analog-to-digital converters, emphasizing only the wanted channel. Thus, the ADCs operate with modest resolution and sample rate, consuming low power. This approach makes portable SDR a reality

Analysis of First-Order Anti-Aliasing Integration Sampler

Performance of the first-order anti-aliasing integration sampler used in software-defined radio (SDR) receivers is analyzed versus all practical nonidealities. The nonidealities that are considered in this paper are transconductor finite output resistance, switch resistance, nonzero rise and fall times of the sampling clock, charge injection, clock jitter, and noise. It is proved that the filter is quite robust to all of these nonidealities except for transconductor finite output resistance. Furthermore, linearity and noise performances are all limited to design of a low-noise and highly linear transconductor.

Noise in passive FET mixers: a simple physical model

White and flicker noise mechanisms in passive FET mixers are explained in intuitive terms, and simple expressions for circuit design are derived. The analysis is validated against simulations and measurement.

A second-order anti-aliasing prefilter for an SDR receiver

A new architecture is presented for a sinc2(f) filter intended to sample channels of varying bandwidth when surrounded by blockers and adjacent bands. Sample rate is programmable from 5 to 40 MHz, and aliases are suppressed by 45 dB or more. The 0.13-mum CMOS circuit consumes 6mA from 1.2V

Injection-Locked Frequency Dividers based on Ring Oscillators with Optimum Injection for Wide Lock Range

Divide-by-2 and divide-by-6 ring oscillators use multi-phase injection to operate from near DC to 1.7 and 1.2 GHz input frequencies, respectively. In 0.13-mum CMOS, the circuits consume 0.25 mA per stage

A Second-Order Antialiasing Prefilter for a Software-Defined Radio Receiver

A new architecture is presented for a sinc2(f) filter intended to sample channels of varying bandwidth when surrounded by blockers and adjacent bands. The sample rate is programmable from 5 to 40 MHz, and aliases are suppressed by 45 dB or more. The noise and linearity performance of the filter is analyzed, and the effects of various imperfections such as transconductor finite output impedance, interchannel gain mismatch, and residual offsets in the channels are studied. Furthermore, it is proved that the filter is robust to the clock jitter. The 0.13- mum CMOS circuit consumes 6 mA from a 1.2-V supply.