Aibin Yan

Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology

This brief presents a double-node-upset-resilient latch (DNURL) design in 22-nm CMOS technology. The latch comprises three interlocked single-node-upset-resilient cells and each of the cells mainly consists of three mutually feeding back Muller C-elements. Simulation results demonstrate the double-node upset resilience and a 73.0% delay-power-area product saving on average compared with the up-to-date DNURL designs.

A Methodology for Characterization of SET Propagation in SRAM-Based FPGAs

This paper presents a methodology for accurate characterization of Single Event Transient (SET) propagation in SRAM-based Field Programmable Gate Arrays (FPGAs): both generation and measurement of SETs are implemented on chip, respectively connected to input port and output port of the test combinational paths. The scheme we developed is mainly based on two circuits: 1) the one is a SET generating circuit for on-chip producing an adjustable pulse with a temporal resolution of near 100 ps; 2) the other is a SET measuring circuit for on-chip measuring pulses with a temporal resolution of near 80 ps and the ability to detect narrow transient pulses of about 300 ps. Based on above methodology, we investigate the effect of traversing seven logic chains with different gate types and multiple chain lengths on pulse widths, i.e., Propagation Induced Pulse Distorting (PIPD). Results demonstrate, when SETs propagate along Look Up Tables (LUTs) in Virtex-6 FPGAs, there is a broadening for negative SETs (1-0-1) while not for positive SETs (0-1-0); in addition, pulse width has no impact on PIPD, and which is linearly proportional to the number of stages.

A transient pulse dually filterable and online self-recoverable latch

This paper presents a transient Pulse Dually Filterable and online Self-Recoverable (referred to as PDFSR) latch. Based on soft error masking property of C-element and using built-in delayed paths combined with a Schmitt inverter, a single event transient (SET) pulse could be dually filtered. Meanwhile, mutually feeding back mechanism of multiple C-elements was constructed to retain data, which makes the latch self-recoverable from a single event upset (SEU). Simulation results have demonstrated the SET filtering ability and SEU resilience at the cost of only 2.0% area-powerdelay-width product increase on average, compared with the similar latches.

HLDTL: High-performance, low-cost, and double node upset tolerant latch design

This paper presents a high-performance, low-cost, and double node upset (DNU) tolerant latch design. The latch mainly constructs from a 3-input Muller C-element at the output stage and a single node upset resilient cell for keeping data, and the cell mainly consists of triple mutual feedback 2-input Muller C-elements, thus the latch is DNU tolerant. Using fewer CMOS transistors, clock gating technique, and high-speed transmission path, the latch also performs with lower cost penalties. Simulation results have demonstrated the DNU tolerability and a ∼97.78% area-power-delay product saving for the latch design on average compared with the DNU tolerant latch designs.

A single event transient detector in SRAM-based FPGAs

This paper presents a novel single event transient (SET) measurement circuit in SRAM-based field programmable gate arrays (FPGAs). Experimental results demonstrate that the new pulse detector is able to onchip measure bipolar pulses with a detection limit of near 150 ps, compared with existing pulse detectors, detection capability and detection precision are effectively improved.