Yiming Ouyang

Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology

This brief presents a double-node-upset-resilient latch (DNURL) design in 22-nm CMOS technology. The latch comprises three interlocked single-node-upset-resilient cells and each of the cells mainly consists of three mutually feeding back Muller C-elements. Simulation results demonstrate the double-node upset resilience and a 73.0% delay-power-area product saving on average compared with the up-to-date DNURL designs.

A Methodology for Characterization of SET Propagation in SRAM-Based FPGAs

This paper presents a methodology for accurate characterization of Single Event Transient (SET) propagation in SRAM-based Field Programmable Gate Arrays (FPGAs): both generation and measurement of SETs are implemented on chip, respectively connected to input port and output port of the test combinational paths. The scheme we developed is mainly based on two circuits: 1) the one is a SET generating circuit for on-chip producing an adjustable pulse with a temporal resolution of near 100 ps; 2) the other is a SET measuring circuit for on-chip measuring pulses with a temporal resolution of near 80 ps and the ability to detect narrow transient pulses of about 300 ps. Based on above methodology, we investigate the effect of traversing seven logic chains with different gate types and multiple chain lengths on pulse widths, i.e., Propagation Induced Pulse Distorting (PIPD). Results demonstrate, when SETs propagate along Look Up Tables (LUTs) in Virtex-6 FPGAs, there is a broadening for negative SETs (1-0-1) while not for positive SETs (0-1-0); in addition, pulse width has no impact on PIPD, and which is linearly proportional to the number of stages.

An improved communication scheme for non-HOL-blocking wireless NoC

Abstract As the wireless interface often requires handling numbers of data simultaneously in wireless network-on-chip, it potentially causes data congestions. The degradation of wireless data transfer can tremendously reduce the efficiency of the network communication. In this paper, virtual output queuing (VOQ) technique has been used to eliminate the head-of-line blocking issue. Moreover, a novel and effective communication scheme has also been introduced to alleviate the traffic load in wireless nodes and hence improving the efficiency of wireless communication. Simulation results indicate that our proposed architecture is advantageous in various aspects including the transfer latency, network throughput and energy consumption.