Cuiyun Jiang

A scheme of test data compression based on coding of even bits marking and selective output inversion

A new scheme of test data compression/decompression, namely coding of even bits marking and selective output inversion, is presented. It first uses a special kind of codewords, odd bits of which are used to represent the length of runs and even bits of which are used to represent whether the codewords finish. The characteristic of the codewords make the structure of decompressor simple. It then introduces a structure of selective output inversion to increase the probability of 0s. This scheme can obtain a better compression ratio than some already known schemes, but it only needs a very low hardware overhead. The performance of the scheme is experimentally confirmed on the larger examples of the ISCAS89 benchmark circuits.

A BIST Scheme Based on Selecting State Generation of Folding Counters

In this paper, a BIST scheme based on selecting state generation of folding counters is presented. LFSR is used to encode the seeds of the folding counters, where folding distances (or indexes) are stored to control deterministic test patterns generation, so that the generated test set is completely equal to the original test set. This scheme solves compression of the deterministic test set and overcomes overlapping and redundancy of test patterns produced by the different seeds. Experimental results prove that it not only achieves higher test data compression ratio, but also efficiently reduces test application time, and that the average test application time is only four percent of that of the same type scheme.

A Methodology for Characterization of SET Propagation in SRAM-Based FPGAs

This paper presents a methodology for accurate characterization of Single Event Transient (SET) propagation in SRAM-based Field Programmable Gate Arrays (FPGAs): both generation and measurement of SETs are implemented on chip, respectively connected to input port and output port of the test combinational paths. The scheme we developed is mainly based on two circuits: 1) the one is a SET generating circuit for on-chip producing an adjustable pulse with a temporal resolution of near 100 ps; 2) the other is a SET measuring circuit for on-chip measuring pulses with a temporal resolution of near 80 ps and the ability to detect narrow transient pulses of about 300 ps. Based on above methodology, we investigate the effect of traversing seven logic chains with different gate types and multiple chain lengths on pulse widths, i.e., Propagation Induced Pulse Distorting (PIPD). Results demonstrate, when SETs propagate along Look Up Tables (LUTs) in Virtex-6 FPGAs, there is a broadening for negative SETs (1-0-1) while not for positive SETs (0-1-0); in addition, pulse width has no impact on PIPD, and which is linearly proportional to the number of stages.

A single event transient detector in SRAM-based FPGAs

This paper presents a novel single event transient (SET) measurement circuit in SRAM-based field programmable gate arrays (FPGAs). Experimental results demonstrate that the new pulse detector is able to onchip measure bipolar pulses with a detection limit of near 150 ps, compared with existing pulse detectors, detection capability and detection precision are effectively improved.

A Test Vector Compression/Decompression Scheme Based on Logic Operation between Adjacent Bits (LOBAB) Coding

A new test vector compression/decompression scheme, namely a scheme of Logic Operation between Adjacent Bits (LOBAB) is presented, which is based on bitwise logic operation between itself and its previous bit. It turns all kinds of series including continuous series, such as a series of all 0s and all 1s, and reversal series, such as a series of 01 and 10, into series of all 0s by logic operation between adjacent bits. On one hand, the two kinds of series, continuous series and reversal series, are both taken into account, which decreases the number of division to the original test data. On the other hand, all series are turned into series of all 0s, which eases the process of encoding and decoding. Compared with other already known schemes this scheme has some characteristics, such as high compression ratio, easy control and implementation. The performance of the algorithm is mathematically analyzed and its merits are experimentally confirmed on the larger examples of the ISCAS89 benchmark circuits.

Optimal LFSR-Coding Test Data Compression Based on Test Cube Dividing

In this paper, a kind of test cube dividing strategy is investigated on which the optimal LFSR-coding scheme is based. The strategy utilizes the fact that the number of specified bits in different test cubes varies widely and the specified bits in a test cube clusters mostly, in which each of the test cubes with high fill rates is divided into two cubes having lower fill rates, and the guiding rule is that one cube consists of odd bits of the original test cube, whereas the second cube is comprised of even bits of the original pattern. The number of specified bits in a new cube is reduced effectively, which makes degree of LFSR needed for encoding it successfully smaller. A LFSR decoder of low complexity is used to outspread the seeds and merge two successively decoded patterns. The experimental results show that compared to the previous techniques, the proposed scheme can achieve higher test data compression ratio. The seeds for LFSR decoding being of the same length, it is convenient to communicate between ATE and circuit under test.