Maoxiang Yi

A BIST Scheme Based on Selecting State Generation of Folding Counters

In this paper, a BIST scheme based on selecting state generation of folding counters is presented. LFSR is used to encode the seeds of the folding counters, where folding distances (or indexes) are stored to control deterministic test patterns generation, so that the generated test set is completely equal to the original test set. This scheme solves compression of the deterministic test set and overcomes overlapping and redundancy of test patterns produced by the different seeds. Experimental results prove that it not only achieves higher test data compression ratio, but also efficiently reduces test application time, and that the average test application time is only four percent of that of the same type scheme.

Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology

This brief presents a double-node-upset-resilient latch (DNURL) design in 22-nm CMOS technology. The latch comprises three interlocked single-node-upset-resilient cells and each of the cells mainly consists of three mutually feeding back Muller C-elements. Simulation results demonstrate the double-node upset resilience and a 73.0% delay-power-area product saving on average compared with the up-to-date DNURL designs.

A Methodology for Characterization of SET Propagation in SRAM-Based FPGAs

This paper presents a methodology for accurate characterization of Single Event Transient (SET) propagation in SRAM-based Field Programmable Gate Arrays (FPGAs): both generation and measurement of SETs are implemented on chip, respectively connected to input port and output port of the test combinational paths. The scheme we developed is mainly based on two circuits: 1) the one is a SET generating circuit for on-chip producing an adjustable pulse with a temporal resolution of near 100 ps; 2) the other is a SET measuring circuit for on-chip measuring pulses with a temporal resolution of near 80 ps and the ability to detect narrow transient pulses of about 300 ps. Based on above methodology, we investigate the effect of traversing seven logic chains with different gate types and multiple chain lengths on pulse widths, i.e., Propagation Induced Pulse Distorting (PIPD). Results demonstrate, when SETs propagate along Look Up Tables (LUTs) in Virtex-6 FPGAs, there is a broadening for negative SETs (1-0-1) while not for positive SETs (0-1-0); in addition, pulse width has no impact on PIPD, and which is linearly proportional to the number of stages.

HLDTL: High-performance, low-cost, and double node upset tolerant latch design

This paper presents a high-performance, low-cost, and double node upset (DNU) tolerant latch design. The latch mainly constructs from a 3-input Muller C-element at the output stage and a single node upset resilient cell for keeping data, and the cell mainly consists of triple mutual feedback 2-input Muller C-elements, thus the latch is DNU tolerant. Using fewer CMOS transistors, clock gating technique, and high-speed transmission path, the latch also performs with lower cost penalties. Simulation results have demonstrated the DNU tolerability and a ∼97.78% area-power-delay product saving for the latch design on average compared with the DNU tolerant latch designs.

A single event transient detector in SRAM-based FPGAs

This paper presents a novel single event transient (SET) measurement circuit in SRAM-based field programmable gate arrays (FPGAs). Experimental results demonstrate that the new pulse detector is able to onchip measure bipolar pulses with a detection limit of near 150 ps, compared with existing pulse detectors, detection capability and detection precision are effectively improved.

NBTI mitigation by M-IVC with input duty cycle and randomness constraints

An improved M-IVC scheme is proposed to mitigate the NBTI aging of circuit in standby mode, in which the input control vectors are randomly generated under constraint of the input duty cycles obtained by genetic algorithm. The experimental results show that compared with the existing M-IVC method, the circuit time delay degradation can be improved by 51.5% on average when S/A is 5/5 and the effectiveness gets better as S/A increases.

Optimal LFSR-Coding Test Data Compression Based on Test Cube Dividing

In this paper, a kind of test cube dividing strategy is investigated on which the optimal LFSR-coding scheme is based. The strategy utilizes the fact that the number of specified bits in different test cubes varies widely and the specified bits in a test cube clusters mostly, in which each of the test cubes with high fill rates is divided into two cubes having lower fill rates, and the guiding rule is that one cube consists of odd bits of the original test cube, whereas the second cube is comprised of even bits of the original pattern. The number of specified bits in a new cube is reduced effectively, which makes degree of LFSR needed for encoding it successfully smaller. A LFSR decoder of low complexity is used to outspread the seeds and merge two successively decoded patterns. The experimental results show that compared to the previous techniques, the proposed scheme can achieve higher test data compression ratio. The seeds for LFSR decoding being of the same length, it is convenient to communicate between ATE and circuit under test.