Aibin Yu

Study of 15µm pitch solder microbumps for 3D IC integration

Developments of ultra fine pitch and high density solder microbumps and assembly process for low cost 3D stacking technologies are discussed in this paper. The solder microbumps developed in this work consist of Cu and Sn, which are electroplated in sequential with total thickness of 10µm; The under bump metallurgy (UBM) pads used here is electroless plated nickel and immersion gold (ENIG) with thickness of 2µm. Accordingly, joining of the two Si chips can be conducted by joining CuSn solder microbumps to ENIG UBM pads or CuSn solder microbumps to CuSn solder microbumps. The first joining can only be done with chip to chip assembly whereas the second joining has the potential for chip to wafer assembly. Assembly of the Si chips is conducted with the FC150 flip chip bonder at different temperatures, times, and pressures and the optimized bonding conditions are obtained. After assembly, underfill process is carried out to fill the gap and a void free underfilling is achieved using an underfill material with fine filler size.

Fabrication of High Aspect Ratio TSV and Assembly With Fine-Pitch Low-Cost Solder Microbump for Si Interposer Technology With High-Density Interconnects

Fabrication of high aspect ratio through silicon vias (TSVs) in a Si interposer and fine pitch solder microbumps on a top Si die is discussed in this paper. Chip stacking result of the Si interposer and the top Si die is also presented. TSVs with 25 μm in pitch and aspect ratio higher than 10 are etched with BOSCH process. To avoid difficulties in wetting the sidewall of the TSVs, bottom-up plating method is used to fill the TSVs with Cu. In order to fill the TSVs from bottom, the TSVs are first sealed from the bottom by plated Cu with plating current of 1 A. The plated Cu is used as a seed layer and bottom-up plating is then conducted with plating current of 0.1 A. Good filling without voids or with only tiny voids has been achieved. Electroless nickel/immersion gold is plated on top of the TSVs as under bump metallurgy pads. On the top Si die, Cu pillars/Sn caps with 16 μm in diameter and 25 μm in pitch are fabricated with electroplating method. After chip stacking, interconnections are formed between them through the solder microbumps and the TSVs.

Fabrication of Silicon Carriers With TSV Electrical Interconnections and Embedded Thermal Solutions for High Power 3-D Packages

This paper presents micro fabrication process and wafer-level integration of a silicon carrier, which consists of two Si chips that are bonded together with evaporated AuSn-solder. There are micro fins and channels fabricated in the Si chip and form the embedded cooling layer after bonding. The embedded cooling layer is connected with an inlet and an outlet to form a fluidic path for heat transfer enhancement. Besides, in the silicon carrier, there are through silicon vias (TSVs) with metal film on sidewall for electrical interconnection. Two or more carriers can then be stacked together with a silicon interposer in between to make up of a stacked cooling module for high power heat dissipation. The advantage of this 3-D stacking method is that it provides a method of simultaneously realizing electrical interconnection and fluidic path and it can extract heat from the constraints of 3-D silicon module chips to surface without external liquid circulation.

Development of Fine Pitch Solder Microbumps for 3D Chip Stacking

Developments of ultra fine pitch and high density solder microbumps for advanced 3D stacking technologies are discussed in this paper. CuSn solder microbumps with 25 ¿m in pitch are fabricated at wafer level by electroplating method and the total thicknesses of the platted Cu and Sn are 10 ¿m. After plating, the micro bumps on the Si chip are reflowed at 265°C and the variation of bump height measured within a die is less than 5%. The under bump metallurgy (UBM) layer on the Si carrier used is electroless plated nickel and immersion gold (ENIG) with total thickness less than 5 ¿m. Assembly of the Si chip and the Si carrier is conducted with the FC150 flip chip bonder at different temperatures, times, and pressures and the optimized bonding conditions are obtained. After assembly, underfill process is carried out to fill the gap and a void free underfilling is achieved using an underfill material with fine filler size.

Si nanophotonics based cantilever sensor

We present design and simulation results of a novel nanomechanical sensor using silicon cantilever embedded with a two-dimensional photonic crystal microcavity resonator. Both of resonant wavelength and resonant wavelength shift could be measured as a function of various physical parameters such as applied force, strain, and displacement. Rather linear relationship is derived for strain and resonant wavelength shift. This new nanomechanical sensor shows promising features for biomolecules detection.

Development of low temperature bonding using in-based solders

In-based solders were chosen for the low temperature bonding at lower than 180degC. Three kinds of bonding types on Au/Cu/Ti/SiO2/Si dies, which were Sn/In and Au/In for Type 1, Au/In and Au/Sn for Type 2, and InSn alloy and InSn alloy for Type 3, were studied expecting that the whole In- solder layer is converted to the mixed intermetallic compound (IMC) phases of In-Cu and In-Au IMCs after bonding below 180degC and annealing at 100~120degC. The IMC in the joints were characterized in terms of the micro structure observations and the compositional analysis with Scanning Electron Microscopy (SEM) and Energy Dispersive X-ray Spectroscopy (EDX), the phase identification with X-ray Diffraction (XRD) and the re-melting temperature with Differential Scanning Calorimetry (DSC). The phase equilibriums of the joints were examined by thermodynamic calculations to understand the re-melting behavior. As a result, complete bonding consisted of only high melting temperature IMCs, Cu11ln9, Cu2In, eta-Cu6Sn5, and Auln2, was successfully made at 120degC followed by annealing at 100degC in Type 3, and at 160degC with annealing for lOhrs or at 180degC without annealing for Type 1, which was confirmed by DSC measurements and explained through thermodynamic calculations.

The role of Ni buffer layer on high yield low temperature hermetic wafer bonding using In/Sn/Cu metallization

Low temperature hermetic wafer bonding using In/Sn interlayer and Au/Ni/Cu metallization as the high-melting-point (HMP) components was reported, wherein the thin Ni layer was introduced as a buffer layer to prevent solder consumption after their deposition. 8 in. wafer to wafer bonding was achieved at 180 °C for 20 min under 5.5 Mpa. Voids free seal joints composed of high temperature intermetallic compounds were obtained with good hermeticity. Present results show that the buffer layer is the key to ensure high yield hermetic wafer bonding when the low-melting-point solder was deposited directly on the HMP component.

Novel piezoelectric actuation mechanism for a gimbal-less mirror in 2D raster scanning applications

In this paper, we present the design, fabrication and measurement results of a 2D scanning mirror actuated by 1 × 10 piezoelectric Pb(Zr,Ti)O3 (PZT) cantilever actuators integrated on a thin silicon beam. A combination of bulk silicon micromachining based on a silicon-on-insulator (SOI) substrate and thin-film surface micromachining on a 5 µm thick Si device layer is used to fabricate the device. Multi-layers of Pt/Ti/PZT/Pt/Ti are deposited as electrode materials. A large silicon mirror plate (5 mm × 5 mm) and a 1 × 10 PZT cantilever array arranged in parallel are formed after the backside release process. The ten PZT cantilever actuators are electrically isolated from one another. The device can operate in three modes: bending, torsional and mixed (or combinational) modes. In bending mode, the first resonant frequency was measured to be 30 Hz and an optical deflection angle of ±8° was obtained when all ten cantilevers were actuated at 9 Vpp. In torsional mode, the resonant frequency was measured to be 89 Hz and an optical deflection angle of ±4.6° was obtained by applying a gradually declining ac voltage started at 8 Vpp to two sets of actuators, where each set comprises five cantilever actuators of the said 1 × 10 array, i.e. 1–5 and 6–10. A 2D raster scanning pattern was achieved in the mixed mode when the bending mode was carried out by cantilever actuators of 4–7 and the torsional modes were exercised by two different sets of cantilever actuators, i.e. 1–3 and 8–10, under opposite biasing direction. This mixed mode operation mechanism demonstrates the first 2D raster scanning mirror-driven beam actuators.

Fabrication of silicon carriers with TSV electrical interconnections and embedded thermal solutions for high power 3-D package

This paper presents micro fabrication process and wafer level integration of a silicon carrier, in which optimized liquid cooling layers are embedded. Two or more carriers can then be stacked together with a silicon interposer in between to make up of a stacked cooling module for high power heat dissipation. Wafer bonding are carried out with AuSn-solder which deposited by evaporation and the shear strength is higher than 27.2 MPa after bonding, which is high enough for application. The advantage of this 3-D stacking method is that it provides a method of simultaneous realizing electrical interconnection and fluidic path between two carriers and it can extract heat from the constraints of 3-D silicon module chips to surface without external liquid circulation.

Retro-Axial VOA Using Parabolic Mirror Pair

This letter presents a design of a microelectromechanical systems variable optical attenuator (VOA) that employs a pair of parabolic mirrors as the retro-reflector, which has obtained a linear relationship over a 62-dB range between the attenuation (in decibels) and the mirror rotation angle (in degrees). The insertion loss measures 0.6 dB thanks to the three-dimentional optical coupling design. The linearity comes from the simultaneous shift and defocus of the laser beam. Compared with the conventional coaxial and cross-axial VOAs, such retro-axial design has the two fibers arranged on the same side and thus facilitates the use of standard packaging formats