Aditya Kumar

Study of 15µm pitch solder microbumps for 3D IC integration

Developments of ultra fine pitch and high density solder microbumps and assembly process for low cost 3D stacking technologies are discussed in this paper. The solder microbumps developed in this work consist of Cu and Sn, which are electroplated in sequential with total thickness of 10µm; The under bump metallurgy (UBM) pads used here is electroless plated nickel and immersion gold (ENIG) with thickness of 2µm. Accordingly, joining of the two Si chips can be conducted by joining CuSn solder microbumps to ENIG UBM pads or CuSn solder microbumps to CuSn solder microbumps. The first joining can only be done with chip to chip assembly whereas the second joining has the potential for chip to wafer assembly. Assembly of the Si chips is conducted with the FC150 flip chip bonder at different temperatures, times, and pressures and the optimized bonding conditions are obtained. After assembly, underfill process is carried out to fill the gap and a void free underfilling is achieved using an underfill material with fine filler size.

Wafer level embedding technology for 3D wafer level embedded package

This paper presents the development of wafer level embedding process for a three dimensional (3D) embedded micro wafer level package (EMWLP). Wafer level embedding process was carried out by using compression molding machine and low-cost granular epoxy molding compound (EMC). Various molding process parameters such as molding time and temperature and three EMCs of different CTEs were analyzed to achieve reliable 3D EMWLP. Several molding process issues, such as warpage, die-sweep, EMC penetration, and die-shift, were faced during embedding process development. A large warpage of more than 1 mm and die-shift of more than 600 µm were found to occur in reconstructed molded wafer. Wafer level embedding process was optimized to reduce warpage and die-shift problems. A significant reduction in warpage (∼ 30 %) and die-shift (∼ 88 %) were achieved after embedding process optimization. The detail of process optimization is presented in the paper. Reconstructed molded wafers were subjected to various reliability tests, such as thermal cycle (TC), moisture sensitivity test-level 3 (MST-L3), and highly accelerated stress test (HAST). Scanning acoustic microscopy (SAM) analysis of molded wafers was carried out to analyze the void formation and delamination in molded wafers. No major void or delamination was observed in reconstructed wafer after molding as well as after reliability tests.

Fabrication of High Aspect Ratio TSV and Assembly With Fine-Pitch Low-Cost Solder Microbump for Si Interposer Technology With High-Density Interconnects

Fabrication of high aspect ratio through silicon vias (TSVs) in a Si interposer and fine pitch solder microbumps on a top Si die is discussed in this paper. Chip stacking result of the Si interposer and the top Si die is also presented. TSVs with 25 μm in pitch and aspect ratio higher than 10 are etched with BOSCH process. To avoid difficulties in wetting the sidewall of the TSVs, bottom-up plating method is used to fill the TSVs with Cu. In order to fill the TSVs from bottom, the TSVs are first sealed from the bottom by plated Cu with plating current of 1 A. The plated Cu is used as a seed layer and bottom-up plating is then conducted with plating current of 0.1 A. Good filling without voids or with only tiny voids has been achieved. Electroless nickel/immersion gold is plated on top of the TSVs as under bump metallurgy pads. On the top Si die, Cu pillars/Sn caps with 16 μm in diameter and 25 μm in pitch are fabricated with electroplating method. After chip stacking, interconnections are formed between them through the solder microbumps and the TSVs.

Embedded wafer level packages with laterally placed and vertically stacked thin dies

Two embedded micro wafer level packages (EMWLP) with (1) laterally placed and (2) vertically stacked thin dies are designed and developed. 3D stacking of thin dies is illustrated as progressive miniaturization driver for multi-chip EMWLP. Both the developed packages have dimensions of 10mm × 10mm × 0.4mm and solder ball pitch of 0.4mm. As part of the work several key processes like thin die stacking, 8 inch wafer encapsulation using compression molding, low temperature dielectric with processing temperature less than 200 °C have been developed. The developed EMWLP components successfully pass 1000 air to air thermal cycling (−40 to 125 °C), unbiased highly accelerated stress testing (HAST) and moisture sensitivity level (MSL3) tests. Developed EMWLP also show good board level TC (≫ 1000 cycles) and drop test reliability results. Integration of thin film passives like inductors and capacitors are also demonstrated on EMWLP platform. Developed thin film passives show a higher Q factor when compared to passives on high resistivity silicon platform. Thermo-mechanical simulation studies on developed EMWLP demonstrate that systemic control over die, RDL and package thicknesses can lead to designs with improved mechanical reliability.

Development of Fine Pitch Solder Microbumps for 3D Chip Stacking

Developments of ultra fine pitch and high density solder microbumps for advanced 3D stacking technologies are discussed in this paper. CuSn solder microbumps with 25 ¿m in pitch are fabricated at wafer level by electroplating method and the total thicknesses of the platted Cu and Sn are 10 ¿m. After plating, the micro bumps on the Si chip are reflowed at 265°C and the variation of bump height measured within a die is less than 5%. The under bump metallurgy (UBM) layer on the Si carrier used is electroless plated nickel and immersion gold (ENIG) with total thickness less than 5 ¿m. Assembly of the Si chip and the Si carrier is conducted with the FC150 flip chip bonder at different temperatures, times, and pressures and the optimized bonding conditions are obtained. After assembly, underfill process is carried out to fill the gap and a void free underfilling is achieved using an underfill material with fine filler size.

A novel method to predict die shift during compression molding in embedded wafer level package

The increased functionality of cellular phones and handheld devices requires system level integration. Thus there is a strong demand in cell phone maker to move to embedded micro wafer level packaging (EMWLP). But the major problem encountered is die shift during compression molding. This paper presents a novel method to predict the die shift during wafer level molding process. A series of parametric studies are performed by changing the die thickness, die pitch distance and top mold chaste compression velocity. The effect of thinning down the chip thickness affects the pressure difference and local shear rate on the chip surfaces. The rate of change of epoxy mold compound fluid pressure across the die top surfaces is not constant. The local shear rate is increasing linearly from the centre of the wafer to the outermost die. From the parametric studies, the die shift is inversely proportional to the die thickness for wafer level molding. Such a phenomenon will reduce the lithography alignment error in the next process. This paper also shows that by reducing die pitch distance of a 5 × 5 mm2, 500 µm thick chip, the die shift decreases by a factor of 12%. In addition, the top mold chaste compression velocity contributes to the die shift by as much as 28% when the velocity is reduced by 50% from 100 µm/sec to 50 µm/sec Finally it is observed from experiment result that the die shift is not constant in all directions.

Residual Stress Analysis in Thin Device Wafer Using Piezoresistive Stress Sensor

In this paper, piezoresistive stress sensors have been used to analyze the residual stress in thin device wafers. For the analysis, device wafers having piezoresistive stress sensors were fabricated. The stress sensors were then calibrated to determine the piezoresistive coefficients. The analysis of residual stress in device wafers was carried out after thinning the device wafers to three different thicknesses ranging from 400 to 100 . The thinning process was performed with the help of commercial wafer back-grinding machine and the complete thinning process included rough grinding, then fine grinding, and finally chemical-mechanical polishing. It was found that wafer back-grinding of device wafers generates a large amount of compressive stress at the surface of the device wafers and the amount of stress increases exponentially with the decrease in wafer thickness. The stress was also measured after mounting the thin device wafers on dicing tape. It was found that the mounting on dicing tape generates tensile stress at the device wafer surface. These trends of stress in the thin device wafers were confirmed with the bending profile of the wafers. A detailed explanation for the development of stresses in the thin device wafer is provided in this paper.

High Quality and Low Loss Millimeter Wave Passives Demonstrated to 77-GHz for SiP Technologies Using Embedded Wafer-Level Packaging Platform (EMWLP)

With the increasing demand for system integration to cater to continuously increasing number of I/Os as well as higher operating frequencies, reconfigured wafer-level packaging, or embedded WLP (EMWLP) is emerging as a promising technology for integration. This platform allows integrated passives to be designed in the redistribution layers using the mold compound as a substrate, which significantly improves the passives performance compared to those of on-chip. In this paper, we present low loss passives on EMWLP platform demonstrated in a 5.5-GHz band pass filter targeted for wireless local area network (WLAN) applications. To ascertain the feasibility of designing for low loss millimeter wave passives on EMWLP, transmission lines were designed and their loss characteristics investigated up to 110 GHz, which are reported here. Subsequently we demonstrate for the first time a narrowband low loss 77-GHz band pass filter on EMWLP platform, with a good correlation obtained between simulation and measurement results. In addition, a temperature dependence characterization was performed on the 77-GHz filter, with little variation in the measured filter characteristics observed.

Evaluation of Stresses in Thin Device Wafer using Piezoresistive Stress Sensor

In this work, piezoresistive stress sensors have been used to evaluate the stresses in thin device wafer. For the evaluation, device wafers having piezoresistive stress sensors were fabricated. The stress sensors were then calibrated to determine the piezoresistive coefficients. The evaluation of stresses in device wafer was carried out after thinning the device wafers to three different thicknesses ranging from 400 ¿m to 100 ¿m. The thinning process was performed with the help of commercial wafer back-grinding machine and the complete thinning process included rough grinding, then fine grinding, and finally polishing. It is found that wafer back-grinding of device wafer generates a large amount of compressive stress at the device wafer surface and the amount of stress increases exponentially with the decrease in wafer thickness. The stresses were also evaluated after mounting the thin device wafers on dicing tape. It is found that the mounting on dicing tape generates tensile stress at the device wafer surface. These trends of stresses in the thin device wafers were confirmed with the bending profile of thin device wafers. A detailed explanation for the development of stresses in the thin device wafer is provided in the paper.

Effect of wafer back grinding on the mechanical behavior of multilayered low-k for 3D-stack packaging applications

To study the effect of back grinding on the mechanical properties of the active side of the die, low-k stacked wafers were grinded to four different thicknesses of 500 mum, 300 mum, 150 mum, and 75 mum by using a commercial grinding process. Nanoindentation and nanoscratch tests were performed using the Nanoindenter XP (MTS Corp. USA) on both the normal (no back grinding) and back grinded samples to analyze the failure loads, modulus, hardness and adhesive/cohesive strength, of the low-k stack. It is found that the back grinding process enhances the mechanical integrity of low-k stack as the back grinded low-k stack exhibited in terms of the higher failure load and cohesive and/or adhesive strength of grinded low-k stack than the normal low-k stack. The TEM cross-section analysis showed that the interfaces in the low-k stack of normal sample are wavy, whereas the interfaces in the low-k stack of back grinded samples are even, especially at the black diamond region. Significant densification of BD films is observed in the case of back grinded sample. Based on these results, it is believed that the thermo-mechanical stresses applied and/or generated during wafer back grinding process affect the microstructure and enhance the mechanical strength of the low-k stack.