D. Pinjala

Development of through silicon via (TSV) interposer technology for large die (21×21mm) fine-pitch Cu/low-k FCBGA package

Because of Moores (scaling/integration) law, the Cu/low-k silicon chip is getting bigger, the pin-out is getting higher, and the pitch is getting finer. Thus, the conventional organic buildup substrates cannot support these kinds of silicon chips anymore. To address these needs, Si interposer with TSV has emerged as a good solution to provide high wiring density interconnection, to minimize CTE mismatch to the Cu/low-k chip that is vulnerable to thermal-mechanical stress, and to improve electrical performance due to shorter interconnection from the chip to the substrate. This paper presents the development of TSV interposer technology for a 21×21 mm Cu/low-k test chip on FCBGA package. The Cu/low-k chip is a 65 nm, 9-metal layer chip with 150 µm SnAg bump pitch of total 11,000 I/O, with via chain and daisy chain for interconnect integrity monitoring and reliability testing. The TSV interposer size is 25×25×0.3 mm with CuNiAu as UBM on the top side, and SnAgCu bumps on the underside. The conventional BT substrate size is 45×45 mm with BGA pad pitch of 1 mm and core thickness of 0.8 mm. Mechanical and thermal modeling and simulation for the FCBGA package with TSV interposer have been performed. TSV interposer fabrication processes and assembly process of the large die mounted on TSV interposer with Pb-free micro solder bumps and underfill have been set up. The FCBGA samples have been subjected to moisture sensitivity test and thermal cycling (TC) reliability assessments.

Study of 15µm pitch solder microbumps for 3D IC integration

Developments of ultra fine pitch and high density solder microbumps and assembly process for low cost 3D stacking technologies are discussed in this paper. The solder microbumps developed in this work consist of Cu and Sn, which are electroplated in sequential with total thickness of 10µm; The under bump metallurgy (UBM) pads used here is electroless plated nickel and immersion gold (ENIG) with thickness of 2µm. Accordingly, joining of the two Si chips can be conducted by joining CuSn solder microbumps to ENIG UBM pads or CuSn solder microbumps to CuSn solder microbumps. The first joining can only be done with chip to chip assembly whereas the second joining has the potential for chip to wafer assembly. Assembly of the Si chips is conducted with the FC150 flip chip bonder at different temperatures, times, and pressures and the optimized bonding conditions are obtained. After assembly, underfill process is carried out to fill the gap and a void free underfilling is achieved using an underfill material with fine filler size.

Fabrication of High Aspect Ratio TSV and Assembly With Fine-Pitch Low-Cost Solder Microbump for Si Interposer Technology With High-Density Interconnects

Fabrication of high aspect ratio through silicon vias (TSVs) in a Si interposer and fine pitch solder microbumps on a top Si die is discussed in this paper. Chip stacking result of the Si interposer and the top Si die is also presented. TSVs with 25 μm in pitch and aspect ratio higher than 10 are etched with BOSCH process. To avoid difficulties in wetting the sidewall of the TSVs, bottom-up plating method is used to fill the TSVs with Cu. In order to fill the TSVs from bottom, the TSVs are first sealed from the bottom by plated Cu with plating current of 1 A. The plated Cu is used as a seed layer and bottom-up plating is then conducted with plating current of 0.1 A. Good filling without voids or with only tiny voids has been achieved. Electroless nickel/immersion gold is plated on top of the TSVs as under bump metallurgy pads. On the top Si die, Cu pillars/Sn caps with 16 μm in diameter and 25 μm in pitch are fabricated with electroplating method. After chip stacking, interconnections are formed between them through the solder microbumps and the TSVs.

Fabrication of Silicon Carriers With TSV Electrical Interconnections and Embedded Thermal Solutions for High Power 3-D Packages

This paper presents micro fabrication process and wafer-level integration of a silicon carrier, which consists of two Si chips that are bonded together with evaporated AuSn-solder. There are micro fins and channels fabricated in the Si chip and form the embedded cooling layer after bonding. The embedded cooling layer is connected with an inlet and an outlet to form a fluidic path for heat transfer enhancement. Besides, in the silicon carrier, there are through silicon vias (TSVs) with metal film on sidewall for electrical interconnection. Two or more carriers can then be stacked together with a silicon interposer in between to make up of a stacked cooling module for high power heat dissipation. The advantage of this 3-D stacking method is that it provides a method of simultaneously realizing electrical interconnection and fluidic path and it can extract heat from the constraints of 3-D silicon module chips to surface without external liquid circulation.

Integrated Liquid Cooling Systems for 3-D Stacked TSV Modules

In this paper, an integrated liquid cooling system for 3-D stacked modules with high dissipation level is proposed. The fluidic interconnects in this system are elaborated and the sealing technique for different fluid interfaces is discussed. Meanwhile, the pressure drop for each part of the system is analyzed. The optimized fluidic interconnects minimizing the pressure drop have been designed and fabricated, and the compact system is integrated. In line with the fluidic interconnect design and analysis, an experimental process for hydraulic characterization of the integrated cooling system is established. The pressure drops for different fluidic interconnects in this system are measured and compared with the analyzed results.

Thermal management of high power dissipation electronic packages: from air cooling to liquid cooling

Performance-driven electronic packaging demands for thermal solutions of high power dissipation such as enhanced air cooling or, alternatively, liquid cooling technologies. This paper reports the characterization of air-cooled vapor chamber heat sink (VCHS) and liquid cooled heat sinks (LCHS) for electronic packages with a targeted power dissipation of 140W. The test vehicle flip chip plastic BGA package (FC-PBGA) involves a thermal test chip with a footprint of 12mm/spl times/12mm mounted on a high density substrate of 40mm/spl times/40mm with 1296 I/Os. The VCHS for characterization consists of a copper vapor chamber attached to the base of an Aluminum heat sink. Five types of thermal interface materials were used in the characterization study. In liquid cooling testing, two Aluminum LCHSs with microchannel width around 0.2mm were designed, fabricated and assembled with the chip. De-ionized water was used as coolant. Thermal measurements were conducted and the system-level thermal analysis shows that, for the VCHS, the overall thermal resistances ranged from 0.72 to 0.61/spl deg/C/W, and maximum power dissipations around 100W are achieved given allowable chip temperature rise of 60/spl deg/C. For the liquid cooling characterization, both thermal resistances and pressure drops were obtained at different flowrates and the system thermal resistances ranged from 0.42 to 0.35/spl deg/C/W at pressure drop less than 0.1 bar, indicating the achievable power dissipation of 140 to 170W. This study reveals that there exist performance limits for the air cooling techniques and liquid cooling technique is a feasible candidate for cooling next-generation high-performance electronic packages.

Pool boiling heat transfer enhancement by surface modification/micro-structures for electronics cooling: a review

Electronics cooling is an important aspect of the microelectronics and microsystem packaging. Liquid cooling involving boiling is emerging as main technique for high heat flux application. Primary issues related to boiling are wall temperature over shoot at boiling incipience and critical heat flux. Heat transfer enhancement has concerned the researchers and practitioners for many decades. This paper reviews experimental works done for boiling enhancement by surface modification and micro-machined structures. Boiling incipient temperature and critical heat flux by various techniques are analyzed. Aim of this review is to design a novel micro-machined structure to enhance boiling and integration of the structure with the chip for cooling 3D stacked module.

Modeling Stress in Silicon With TSVs and Its Effect on Mobility

With the most popular electronic products being the slimmest ones with the highest functionality, the ability to thin, stack, and interconnect chips is becoming more important. One method to accomplish this is by using the through silicon via (TSV). This is a means of electrical connection in 3-D stacked devices that saves space and shortens the electrical interconnect length, improving electrical performance. Unfortunately, the large mismatch between the coefficients of thermal expansion (CTE) of copper (17.5 × 10-6/°C) and silicon (2.5 × 10-6/°C) has made the TSV a reliability concern. A mismatch in CTE translates to a mismatch in thermal strain when the wafer is subjected to large temperature loadings during fabrication. This local thermal mismatch also induces stresses on the silicon surface around the vias which can affect the mobility of the silicon. In this paper, the thermal stresses and strains induced on silicon due to the proximity of copper vias have been investigated for various geometries (via diameter, via pitch, silicon thickness, stacking layers) using finite element modeling. These results should be useful for: 1) designing substrates with TSVs such that mobility in the active devices are not affected by the presence of TSVs, and 2) understanding the limitations of stacking chips with respect to stress in silicon as well as joint reliability.

Thermal characterization of vias using compact models

Thermal vias and balls are key elements in plastic ball grid array (PBGA) package thermal design as they enhance the package performance. Simulation is a versatile design optimization tool for characterizing the thermal vias and balls. However, the finer geometric details of the vias require excessive memory and modeling and simulation time. Different modeling concepts are being tried in the industry to include finer geometries in the package. This paper shows a methodology of developing compact thermal via models and validating the same with detailed models. The accuracy of compact thermal via models with respect to the detailed models has been determined using PBGA 352 as the test vehicle. It is found that the accuracy is within 3%. The simulation models of PBGA 352 have been validated by measurements and found that the accuracy of model is within 10%. Two and four layer PBGA 352s with different via configurations have been characterized with compact thermal via models, and design guidelines for PBGA 352 packages have been obtained.

3-D Packaging With Through-Silicon Via (TSV) for Electrical and Fluidic Interconnections

In this paper, a liquid cooling solution has been reported for 3-D package in package-on-package format. A high heat dissipating chip is mounted on a silicon carrier, which has copper through-silicon via (TSV) for electrical interconnection and hollow TSV for fluidic circulation. Heat transfer enhancement structures have been embedded in the chip carrier. Cooling liquid, de-ionized water is circulated through the chip carrier and heat from the chip is extracted. The fluidic channels are isolated from electrical traces using hermetic sealing. The research work has demonstrated liquid cooling solution for 100 W from one stack and total of 200 W from two stacks of the package. The fluidic interconnections and sealing techniques have been discussed.