Akifumi Kawahara
Panasonic
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Publication
Featured researches published by Akifumi Kawahara.
international solid-state circuits conference | 2012
Akifumi Kawahara; Ryotaro Azuma; Yuuichirou Ikeda; Ken Kawai; Yoshikazu Katoh; Kouhei Tanabe; Toshihiro Nakamura; Yoshihiko Sumimoto; Naoki Yamada; Nobuyuki Nakai; Shoji Sakamoto; Yukio Hayakawa; Kiyotaka Tsuji; Shinichi Yoneda; Atsushi Himeno; Kenichi Origasa; Kazuhiko Shimakawa; Takeshi Takagi; Takumi Mikawa; Kunitoshi Aono
Nonvolatile memories with fast write operation at low voltage are required as storage devices to exceed flash memory performance. We develop an 8Mb multi-layered cross-point ReRAM macro with 443MB/S write throughput (64b parallel write per 17.2ns cycle), which is almost twice as fast as existing methods, using the fast-switching performance of TaOχ ReRAM and the following three techniques to reduce the sneak current in bipolar type cross-point cell array structure in an 0.18μm process. First, memory cell and array technologies reduce the sneak current with a newly developed bidirectional diode as a memory cell select element for the first time. Second, we use a hierarchical bitline (BL) structure for multi-layered cross-point memory with fast and stable current control. Third, we implement a multi-bit write architecture that realizes fast write operation and suppresses sneak current. This work is applicable to both high-density stand-alone and embedded memory with more stacked memory arrays and/or scaling memory cells.
international solid-state circuits conference | 2013
Akifumi Kawahara; Ken Kawai; Yuuichirou Ikeda; Yoshikazu Katoh; Ryotaro Azuma; Yuhei Yoshimoto; Kouhei Tanabe; Zhiqiang Wei; Takeki Ninomiya; Koji Katayama; Ryutaro Yasuhara; Shunsaku Muraoka; Atsushi Himeno; Naoki Yoshikawa; Hideaki Murase; Kazuhiko Shimakawa; Takeshi Takagi; Takumi Mikawa; Kunitoshi Aono
Resistive RAM (ReRAM) has been recently developed for applications that require higher speed and lower voltage than Flash memory is able to provide. One of the applications is micro-controller units (MCUs) or SoCs with several megabits of embedded ReRAM. Another is solid-state drives (SSDs) where a combination of higher-density ReRAM and NAND flash memory would achieve high-performance and high-reliability storage [1], suitable for server applications for future cloud computing. ReRAM is attractive for several reasons. First, it operates at high speed and low voltage. Second, it enables high density due to the simple structure of the resistive element (RE) [2]. Third, it is immune to external environment such as magnetic fields or radiation, since the resistive switching is based on the redox reaction [3].
international conference on ic design and technology | 2014
Ken Kawai; Akifumi Kawahara; Ryutaro Yasuhara; Shunsaku Muraoka; Zhiqiang Wei; Ryotaro Azuma; Kouhei Tanabe; Kazuhiko Shimakawa
ReRAM is increasingly being developed for applications that require higher speeds and lower voltages than flash memory. We have found TaOx to have high performance and high reliability. However one of the phenomena observed in ReRAM is that each resistance after Set and Reset varies during every cycle. To stabilize resistive switching, the key is to limit these variations in resistance. In ReRAM, a conductive filament (CF) is created by the forming pulse. Resistive switching in the CF is based on reduction and oxidization using this voltage pulse. This paper reviews a hopping percolation model which we have proposed for the switching process, and this paper proposes an automatic forming circuit using our newly-developed externally-scalable forming pulse (ESF) scheme. In this CF model, conductive paths show different conductivities caused by the formation of different percolation networks that link hopping sites. Larger CFs show greater variation in resistance due to the many possible combinations of percolation networks. This makes it important to develop a forming technique that limits CFs to their optimal size. Forming is based on dielectric breakdown, so the pulse width ranges over approximately three orders. The automatic forming circuit detects, bit by bit, whether forming is over, and stops the forming pulse after a specified period. A forming pulse is then generated, using an external clock, to cover the range of pulse widths. This allows the filament size to be controlled to ensure it is uniform for all of the bits in the circuit, at the cost of only a small area overhead.
symposium on vlsi circuits | 2015
Yukio Hayakawa; Atsushi Himeno; Ryutaro Yasuhara; W. Boullart; Emma Vecchio; T. Vandeweyer; T. Witters; D. Crotti; M. Jurczak; Satoru Fujii; Shigeru Ito; Yoshio Kawashima; Yuuichirou Ikeda; Akifumi Kawahara; Ken Kawai; Zhiqiang Wei; Shunsaku Muraoka; Kazuhiko Shimakawa; Takumi Mikawa; Shinichi Yoneda
Archive | 1995
Akifumi Kawahara; Toshiki Mori
Archive | 2003
Masatoshi Shinagawa; Akifumi Kawahara; Tetsuyuki Fukushima; Masakazu Kurata; Manabu Komiya
Archive | 1996
Tetsuyuki Fukushima; Akifumi Kawahara; Tsuyoshi Nanba; Masahiko Matsumoto; Toshio Nishimoto; Nobuyuki Ikeda; Yuji Judai; Tatsumi Sumi; Koji Anta; Tatsuo Otsuki
symposium on vlsi circuits | 1996
T. Fukushima; Akifumi Kawahara; T. Nanba; M. Matsumoto; T. Nishimoto; N. Ikeda; Y. Judai; Tatsumi Sumi; T. Otsuki
Archive | 2012
Kazuhiko Shimakawa; Akifumi Kawahara; Ryotaro Azuma; Ken Kawai
Archive | 2012
Akifumi Kawahara; Ryotaro Azuma; Kazuhiko Shimakawa; Kouhei Tanabe