Pierre-Yves Lesaicherre

Ultrathin Tantalum Oxide Capacitor Dielectric Layers Fabricated Using Rapid Thermal Nitridation prior to Low Pressure Chemical Vapor Deposition

We describe the formation of ultrathin tantalum oxide capacitors, using rapid thermal nitridation of the storage-node polycrystalline-silicon surface prior to low pressure chemical vapor deposition of tantalum oxide. The amorphous tantalum oxide film is deposited on the nitrided polysilicon surface using penta-ethoxy-tantalum [Ta(OC 2 H 5 ) 5 ] and oxygen (O 2 ) gas mixture at 410 o C. The films are annealed at 600-900 o C in dry O 2 . Densification of the as-deposited film by annealing in dry O 2 is indispensable to the formation of highly reliable ultrathin tantalum oxide capacitors. During this densification, CH 4 and H 2 O desorb from the as-deposited film, and the film crystallizes into an orthorhombic structure

Structural and electrical characterization of SrTiO3 thin films prepared by metal organic chemical vapor deposition

SrTiO3 thin films were prepared on Si and Pt/TaOx/Si substrates by Sr(DPM)2/Ti(i-OC3H7)4/O2/Ar chemical vapor deposition (CVD), using a simple vaporizing-and-transport source delivery system. A thickness uniformity of ±5.6% and a composition uniformity of ±2.7% were obtained. The dielectric constant was 210 for 110 nm thick SrTiO3 films (Sr/(Sr+Ti)=0.5) annealed at 600°C for 2 hours. An SiO2 equivalent thickness of 1.1 nm was obtained for 40 nm thick SrTiO3 films, and leakage current densities were 6×10-8 A/cm2 at 1.0 V and 5×10-7 A/cm2 at 1.65 V. The structural and electrical properties were affected by the film composition.

Chemical Vapor Deposition of ( Ba , Sr ) TiO3

SrTiO 3 and (Ba, Sr)TiO 3 thin films were fabricated on Si and Pt/TaO 2 /Si substrates by chemical vapor deposition (CVD) using Sr(DPM) 2 , Ba(DPM) 2 , Ti(O-i-C 3 H 7 ) 4 , and O 2 where DPM is dipivaloylmethanate or formally 2,2,6,6-tetramethyl-3,5-heptanedionate. The deposition system was operated in both thermal CVD mode and electron cyclotron resonance (ECR) plasma CVD mode. Variations in individual Sr and Ti deposition rates with differing deposition conditions were investigated. The SrTiO 3 and (Ba, Sr)TiO 3 films were characterized with a view to discussing the step-coverage, crystal structure, and electrical properties. The step-coverage over the 300 nm wide SiO 2 lines, with 500 nm height and 500 nm spacing, was 30 to 40%. The 40 to 100 nm SrTiO 3 films, through the postdeposition annealing process, showed dielectric constants >140 with a leakage current density level <10 -7 A/cm at 1 V. The prospects for applying the CVD (Ba, Sr)TiO 3 films to giga-bit dynamic random access memory storage capacitors are discussed

A stacked capacitor technology with ECR plasma MOCVD (Ba,Sr)TiO/sub 3/ and RuO/sub 2//Ru/TiN/TiSi/sub x/ storage nodes for Gb-scale DRAMs

A Gb-scale DRAM stacked capacitor technology with (Ba,Sr)TiO/sub 3/ thin films is described, The four-layer RuO/sub 2//Ru/TiN/TiSi/sub x/, storage node configuration allows 500/spl deg/C processing and fine-patterning down to the 0.20 /spl mu/m size by electron beam lithography and reactive ion etching. Good insulating (Ba/sub 0.4/Sr/sub 0.6/)TiO/sub 3/ (BST) films with an SiO/sub 2/ equivalent thickness of 0.65 nm on the electrode sidewalls and leakage current of 1/spl times/10/sup -/6 A/cm/sup 2/ at 1 V are obtained by ECR plasma MOCVD without any post-deposition annealing, A lateral step coverage of 50% for BST is observed on the 0.2 /spl mu/m size storage node pattern, and the BST thickness on the sidewalls is very uniform, thanks to the ECR downflow plasma. Using this stacked capacitor technology, a sufficient cell capacitance of 25 fF for 1 Gb DRAMs can be achieved in a capacitor area of 0.125 /spl mu/m/sup 2/ with only the 0.3 /spl mu/m high-storage electrodes.

SrTiO3 thin films by mocvd for 1 gbit DRAM application

Abstract Three important aspects of the preparation of SrTiO3 thin films by MOCVD are discussed in detail in view of the application of these films as the capacitor dielectric of Gbit-scale DRAMs: CVD reactions in the Sr(DPM)2-Ti(i-OC3H7)4-O2 system, step coverage and relations between microstructure and electrical properties. The effect of the substrate temperature on the Sr and Ti deposition rates was first investigated for thermal and ECR CVD SrTiO3 films. SrO and TiO2 deposition by thermal CVD above 550°C were found to be controlled by the surface reaction and gas transport, respectively, whereas both SrO and TiO2 deposition are controlled by gas transport for ECR CVD at 450 to 600°C. The influence of the Sr and Ti deposition regimes on the step coverage of SrO, TiO2 and SrTiO3 were then assessed. SrO films prepared by thermal CVD at 600°C exhibited the best step coverage, indicating that a relation exists between reaction controlled deposition and good step coverage. The effect of the film compositio...

An ECR MOCVD (Ba,Sr)TiO/sub 3/ based stacked capacitor technology with RuO/sub 2//Ru/TiN/TiSi/sub x/ storage nodes for Gbit-scale DRAMs

A high dielectric constant (Ba,Sr)TiO/sub 3/ [BST] based stacked capacitor with new RuO/sub 2//Ru/TiN/TiSi/sub x/ storage nodes was developed for Gbit-scale DRAMs. Good insulating BST films with a small t/sub eq/ of 0.65 nm on the electrode sidewalls were obtained by ECR MOCVD. The four-layer storage node allows 500/spl deg/C processing and fine-patterning down to 0.20 /spl mu/m by EB lithography and RIE. A cell capacitance of 25 fF in 0.125 /spl mu/m/sup 2/ is achieved using 0.3 /spl mu/m-high storage electrodes for 1 Gbit DRAMs.

A Gbit-scale DRAM stacked capacitor technology with ECR MOCVD SrTiO/sub 3/ and RIE patterned RuO/sub 2/TiN storage nodes

A new stacked capacitor technology with high permittivity ECR MOCVD SrTiO/sub 3/ films on 1 Gbit compatible RuO/sub 2/TiN storage nodes was developed for Gigabit-scale DRAMs. A cell capacitance of 25 fF and leakage current density of 8/spl times/10/sup -7/ A/cm/sup 2/ can be achieved with this capacitor technology, using 0.5 /spl mu/m high stacked storage electrodes in a 0.125 /spl mu/m/sup 2/ capacitor area. Fine storage RuO/sub 2/TiN electrodes were patterned down to 0.2 /spl mu/m by electron beam lithography and RIE using an O/sub 2/-based etching mixture. A new low temperature ECR MOCVD technique was also developed to prepare highly reliable SrTiO/sub 3/ films to be used on the storage electrode sidewalls.<<ETX>>

Low temperature deposition of (Ba, Sr)TiO3 films by electron cyclotron resonance plasma chemical vapor deposition

(Ba, Sr)TiO 3 films deposited by electron cyclotron resonance plasma chemical vapor deposition at 450°C and 500°C are investigated. The crystallinity, evaluated by X-ray diffraction and by measuring grain size, and electrical properties of films were evaluated for changes in deposition temperature, deposition rate, and Ba content, without a post-deposition annealing. Slower deposition rates as well as higher deposition temperatures were found to improve film crystallinity. Evaluation of electrical properties and film crystallinity revealed that the optimum Ba content of a film deposited at 500°C was 0.4. A 27nm thick film deposited on a Pt substrate at 500°C and at 1.1 nm/min with a Ba content of 0.4 exhibited a SiO 2 equivalent thickness of 0.65 nm and a leakage current density of 4.6 x 10 -7 A/cm 2 at 1V. The film composition was found to be sufficiently uniform throughout, i.e., from the top to the side of the films on a stacked bottom electrode.

A gbit-scale dram stacked capacitor with ECR MOCVD SrTiO3 over RIE patterned RuO2/TiN storage nodes

Abstract The capacitor requirements for Gbit-scale DRAMs are discussed in detail. The choice of SrTiO3 thin films over a stacked RuO2/TiN structure for the 1 Gbit DRAM is explained, and particular emphasis is put on the necessity of a stacked capacitor structure and on the selection of a suitable electrode material. The influence of film composition, film thickness and substrate temperature on the properties of ECR MOCVD SrTiO3 films is then presented. Maximum permittivity and low leakage current density were obtained for stoichiometric composition, Sr/Ti = 1·0. A thickness of at least 400 A was found to be necessary to obtain SrTiO3 films with sufficient electrical properties. A substrate temperature of 450°C was found to be a suitable temperature for direct deposition of crystallized SrTiO3 and no degradation of the RuO2/TiN bottom electrode structure. A new reactive ion etching process was developed to pattern RuO2/TiN nodes. The key characteristics of this process are the use of an SOG mask, the choic...

A stacked capacitor with an MOCVD-(Ba,Sr)TiO/sub 3/ film and a RuO/sub 2//Ru storage node on a TiN-capped plug for 4 Gbit DRAMs and beyond

A stacked high-/spl epsiv//sub r/ capacitor is fabricated using a 550/spl deg/C-process-tolerant RuO/sub 2//Ru storage node on a TiN-capped plug and an ECR plasma MOCVD (Ba,Sr)TiO/sub 3/ (BST) thin film with small SiO/sub 2/ equivalent thickness (t/sub eq/) of 0.40 nm. The contact resistance (Rc) of a 0.15 /spl mu/m diameter (/spl phi/) contact is as low as 50 k/spl Omega/. With this capacitor technology, a cell capacitance (Cs) of 25 fF is achieved in projected areas of 0.055 /spl mu/m/sup 2/ for 4 Gbit DRAMs and 0.031 /spl mu/m/sup 2/ for 16 Gbit DRAMs with 0.25 /spl mu/m- and 0.37 /spl mu/m-high storage nodes.