Akihiro Noriki

Three-Dimensional Hybrid Integration Technology of CMOS, MEMS, and Photonics Circuits for Optoelectronic Heterogeneous Integrated Systems

We have developed a new 3-D hybrid integration technology of complementary metal-oxide-semiconductors, microelectromechanical systems (MEMS), and photonics circuits for optoelectronic heterogeneous integrated systems. We have overcome the fabrication difficulties of optoelectromechanical and microfluidics hybrid integration. In order to verify the applied 3-D hybrid integration technology, we fabricated a 3-D optoelectronic multichip module composed of large-scale integration (LSI), MEMS, and photonics devices. The electrical chips of amplitude-shift keying (ASK) LSI, passive, and pressure-sensing MEMS were mounted onto an electrical Si interposer with through-silicon vias (TSVs) and microfluidic channels. Photonics chips of vertical-cavity surface-emitting lasers and photodiodes were embedded into an optical Si interposer with TSVs. The electrical and optical interposers were precisely bonded together to form a 3-D optoelectronic multichip module. The photonics and electrical devices could communicate via TSVs. The photonics devices could be connected via an optical waveguide formed onto the optical interposer. Microfluidic channels were formed into the interposer by a wafer-direct bonding technique for heat sinking from high-power LSIs. In this paper, we evaluated the basic functions of individual chips of LSI, MEMS, and photonics devices as they were integrated into the 3-D optoelectronic multichip module to verify the applied 3-D hybrid integration technology. LSI, passive, MEMS, and photonics devices were successfully implemented. The 3-D hybrid integration technology is capable of providing a powerful solution for realizing optoelectronic heterogeneous integrated systems.

Three-dimensional integration technology based on reconfigured wafer-to-wafer and multichip-to-wafer stacking using self-assembly method

We demonstrate two types of three-dimensional (3D) integration using chip self-assembly techniques with liquid surface tension. In reconfigured wafer-to-wafer 3D integration, many different sizes of chips having In/Au microbumps with/without TSV (through-silicon via) were temporarily placed by self-assembly on a reconfigured wafer in a back-to-face manner. The many chips can be then simultaneously transferred to an LSI wafer that is fully faced with the reconfigured wafer and has the same microbump array patterns to the self-assembled chips. On the other hand, in multichip-to-wafer 3D integration, Si chips having In/Au microbumps with sizes of 5 µm and 10 µm were directly self-assembled on another LSI wafer having the same In/Au microbumps in a face-to-face manner. After the self-assembly, these chips can be bonded at 200 °C without applying mechanical pressure. In both of the self-assembly-based 3D integration, the chips were precisely aligned and bonded to the LSI wafers through the microbump-to-microbump interconnection. We obtained good electrical characteristics using the microbump daisy chains formed between the self-assembled chips and the wafers.

New heterogeneous multi-chip module integration technology using self-assembly method

We have newly proposed heterogeneous multi-chip module integration technologies in which MEMS and LSI chips are mounted on Si or flexible substrates using a self-assembly method. A large numbers of chips were precisely and simultaneously self-assembled and bonded onto the substrates with high alignment accuracy of approximately 400 nm. Thick MEMS and LSI chips with a thickness of more than 100 mum were electrically connected by unique lateral interconnections formed crossing over chip edges with large step height. We evaluated fundamental electrical characteristics using daisy chains formed crossing over test chips which were face-up bonded onto the substrates by the self-assembly. We obtained excellent characteristics in these daisy chains. In addition, RF test chips with amplitude shift keying (ASK) demodulator and signal processing circuits were self-assembled onto the substrates and electrically connected by the lateral interconnections. We confirmed that these test chips work well.

3D heterogeneous opto-electronic integration technology for system-on-silicon (SOS)

We proposed 3D heterogeneous opto-electronic integration technology for system-on-silicon (SOS). In order to realize 3D opto-electronic integrated system-on-silicon (SOS), we developed novel heterogeneous integration technology of LSI, MEMS and optoelectronic devices by implementing 3D heterogeneous opto-electronic multi-chip module composed with LSI, passives, MEMS and optoelectronic devices. The electrical interposer mounted with amplitude shift keying (ASK) LSI, LC filter and pressure-sensing MEMS chips and the optical interposer embedded with vertical-cavity surface-emitting laser (VCSEL) and photodiode (PD) chips are precisely bonded to form 3D opto-electronic multi-chip module. Opto-electronic devices are electrically connected via through-silicon vias (TSVs) which were formed into the interposers. Micro-fluidic channels are formed into the interposer by wafer direct bonding technique. 3D heterogeneous opto-electronic multi-chip module is successfully implemented for the first time.

Impact of remnant stress/strain and metal contamination in 3D-LSIs with through-Si vias fabricated by wafer thinning and bonding

Wafer thinning and formation of through-Si via (TSV) and metal microbump are key processes in 3D LSI fabrication. However, it might introduce mechanical stress and crystal defects in thinned wafers. In addition, Cu for TSV and microbump might introduce metal contamination in thinned Si substrate. Then the impact of mechanical stress and metal contamination in the thinned Si substrate has been investigated. The remnant stress left after wafer thinning was evaluated by micro-Raman spectroscopy (µRS) and XPS. It was found that the mechanical stress remained in the back surface of Si substrate after wafer thinning and a part of this mechanical stress appeared in the surface of Si substrate. The metal contamination in such thinned Si substrate has been evaluated by a C-t method. It was found that the carrier generation lifetime was degraded by Cu diffused into Si substrate at relatively low temperature of 200 °C. The mechanical stress/strain in the thinned Si substrate after wafer bonding was also evaluated to investigate the influences of metal microbumps to the thinned Si substrate. It was found that the local mechanical stress was generated in the Si substrate surface by the microbumps. This local stress caused a 3% change in the ON current of MOS transistor.

10 µm fine pitch Cu/Sn micro-bumps for 3-D super-chip stack

We develop novel micro-bumping technology to realize small size, fine pitch and uniform height Cu/Sn bumps. Electroplated-evaporation bumping (EEB) technology, which is a combination of Cu electroplating and Sn evaporation, is developed to achieve uniform height of Cu/Sn bumps. We develop CMOS compatible dry etching processes for removing sputtered Cu/Ta layers to achieve small size and fine pitch Cu/Sn bump. 5 µm square and 10 µm pitch Cu/Sn micro-bumps are successfully fabricated for the first time. Bump height variation is 5 µm ±3 % (95%, 2σ), which is uniform compared to electroplated Cu/Sn bumps. We evaluate micro-joining characteristics of Cu/Sn micro-bumps. Good I–V characteristics are measured from the daisy chain consisting of 1500 bumps with 10 µm square and 20 µm pitch. Resistance of Cu/Sn bump is 35 mΩ/bump, which is very low value compared to electroplated Cu/Sn bumps.

Through-Silicon Photonic Via and Unidirectional Coupler for High-Speed Data Transmission in Optoelectronic Three-Dimensional LSI

We develop Si-core through-silicon photonic via (TSPV) and unidirectional coupler for low-loss and high-speed data transmission in an optoelectronic 3-D LSI. The TSPVs, comprising a Si-core and SiO2 cladding, were fabricated simultaneously with Cu TSVs. The characteristics of light confinement of the TSPV were measured using a near-field pattern measurement. The spot light area was well confined within the TSPV without interference from the lights. The optical intensity that passed through the TSPV was 20% higher than that which passed through the Si substrate. The unidirectional optical coupler with two mirrors showed higher coupling efficiency. Laser light can be efficiently propagated to a planar Si waveguide through the TSPV and the unidirectional coupler.

Through Silicon photonic via (TSPV) with Si core for low loss and high-speed data transmission in opto-electronic 3-D LSI

To realize very high performance computing system, we have proposed a novel opto-electronic 3-D LSI in which both electrical and optical devices are integrated. For realizing such opto-electronic 3-D LSI, through Si photonic via (TSPV) is indispensable for vertical light transmission. In this work, we fabricated the TSPV comprising Si core and epoxy cladding. We measured near field patterns (NFP) of laser light passed through the TSPV to evaluate its light confinement effect. From the results of NFP measurement, we confirmed that the laser light was successfully confined and propagated in the Si core region of the TSPV. We successfully developed a fabrication process to form both the TSPV and TSV simultaneously. The size of the fabricated TSPV and TSV was 20μm×20μm and 16μm×16μm, respectively.

Cu lateral interconnects formed between 100-µm-thick self-assembled chips on flexible substrates

A very new interconnection method, namely Cu lateral interconnection is proposed and tested for the heterogeneous multi-chip module integration in which MEMS and LSI chips are self assembled onto the flexible substrate. Here, the lateral interconnects runs between a few hundred microns thick chip and the Si or flexible substrates as well as at inter chip level. These Cu lateral interconnects were fabricated via conventional electroplating technique. As formed single as well as daisy chain lateral interconnects (both are crossing over the thick test chips that are face-up bonded onto the flexible substrates by self-assembly) were characterized for their electrical characteristics. We have obtained a low resistance values for the Cu lateral interconnects which are close to the calculated values. Further, a module contains RF test chips that are interconnected by this unique Cu lateral interconnections has been tested for the operation.

Temporary spin-on glass bonding technologies for via-last/backside-via 3D integration using multichip self-assembly

In this study, we proposed and demonstrated self-assembly-based via-last/backside-via 3D integration using a temporary spin-on glass (SOG) bonding technology. A hydrogenated amorphous silicon (a-Si:H) was employed as a debonding layer. Known good dies (KGDs) were precisely self-assembled right side up on an electrostatic carrier wafer by surface tension of water, and then, the KGDs were fixed by applying DC voltage to the carrier. After that, the KGDs were temporarily bonded and transferred to another support glass wafer on which the a-Si:H and SOG layers were deposited. After multichip thinning, Cu-TSVs were formed on the KGDs. The resulting TSV daisy chains showed good electrical characteristics. The KGDs can be debonded with a 308-nm laser and transferred again to target interposer wafers.