Akio Kawabata

Robustness of CNT Via Interconnect Fabricated by Low Temperature Process over a High-Density Current

We fabricated a carbon nanotube (CNT) via interconnect and evaluated its robustness over a high-density current. CNTs were synthesized at temperatures as low as 365 °C, which is probably the lowest for this application, without degrading the ultra low-k interlayer dielectrics (k = 2.6). We measured the electrical properties of CNT vias as small as 160 nm in diameter and found that a CNT via was able to sustain a current density as high as 5.0×106 A/cm2 at 105 °C for 100 hours without any deterioration in its properties.

Electrical Properties of Carbon Nanotube Via Interconnects Fabricated by Novel Damascene Process

We studied the electrical properties of a carbon nanotube (CNT) via interconnect fabricated by a novel damascene process which is mostly compatible with conventional Cu interconnects. It was found that the resistance of 60-nm-height vias was independent of temperatures as high as 423 K, which suggests that the carrier transport is ballistic. The obtained resistance of 0.05 Omega for 2.8-mum-diameter vias is the lowest value ever reported. From the via height dependence of the resistance, the electron mean free path was estimated to be about 80 nm, which is similar to the via height predicted for 32-nm technology node (year 2013). This indicates that it will be possible to realize CNT vias with ballistic transport for 32-nm technology node and below.

Associative Memory for Nearest-Hamming-Distance Search Based on Frequency Mapping

The developed associative-memory architecture utilizes a mapping operation of the Hamming distances into frequency space with ring oscillators programmable in discrete frequency steps. As a result fast word-parallel search of the nearest Hamming distance with low power consumption is obtained. Additionally, high robustness against fabrication-related variations of the MOSFET characteristics is achievable by design because the size of the frequency steps is a freely selectable design parameter which can be adjusted to compensate the variation magnitude. A quantitative analysis of within-die variation effects on the reliability of the associative-memory architecture is presented and guidelines for the choice of the design parameters at a given magnitude of the variation effects are derived. Feasibility and performance of this associative-memory architecture are experimentally evaluated with a VLSI design in 180 nm CMOS technology containing 64 reference patterns each consisting of 256 bits. The fabricated chip is correctly operating down to low supply voltages (Vdd) of 0.7 V. The power dissipation is less than 36.5 mW and 307 μW at supply voltages of 1.8 V (nominal supply) and 0.7 V, respectively. Measured search reliability is found to be in agreement with measured variations of the important design parameters and expectations from the variation analysis. In comparison to previously reported digital associative-memory designs, the achieved power dissipation is more than 5 times smaller, while the average search speed is only slightly improved. For Vdd = 1.8 V the search time ranges from a minimum of 50 ns at Hamming distance 0 to a maximum of 245 ns for the largest Hamming distance 255.

High-current reliability of carbon nanotube via interconnects

We have improved the high-current reliability of carbon nanotube (CNT) via interconnects by chemical mechanical polishing (CMP) and vacuum in situ metal deposition processes. These processes enable us to decrease the contact resistance of a CNT via to the upper and lower Cu lines, and also increase the number of CNTs contributing to current flow. Consequently, the current density per CNT was decreased, and current tolerance properties were improved. As a result, the CNTs via interconnects were able to withstand a high current density of 4×107 A/cm2 per via, i.e., 1.7×108 A/cm2 per CNT. In addition, we found that the failure mode of Cu-line/CNT-via/Cu-line interconnects with a CNT density of 3×1011 tubes/cm2 was the slit void formation at the Cu line under the via, which is similar to that of Cu via interconnects. Furthermore, we discussed how to further increase the tolerance of electromigration (EM), taking advantage of their high thermal conductivity.

Long Length, High-Density Carbon Nanotube Film Grown by Slope Control of Temperature Profile for Applications in Heat Dissipation

We have developed a new growth method for a film of dense, vertically aligned carbon nanotubes (CNTs). We varied the slope of the growth temperature profile between 450 and 800 °C. By using the method with an Fe/Ti catalyst, the filling factor of the CNT film was measured to be 0.28, which is 20 times denser than that in the case where conventional CVD growth is utilized. We name this growth method the slope control of temperature profile (STEP) growth. Another feature of CNT films obtained by STEP growth is their mirror like surfaces. This allows for the measurement of the thermal conductivity by a pulse optical heating thermoreflectance method. The maximum thermal conductivity of the STEP-grown CNT film was 260 W m-1 K-1, which is higher than those of a solder and Si. This result suggests that STEP-grown CNT films are effective heat dissipation materials and can be used as thermal interface material (TIM) and thermal through silicon via (TSV).

High-Quality GaAs Films on Si Substrates Grown by Atomic Hydrogen-Assisted Molecular Beam Epitaxy for Solar Cell Applications

Minority carrier lifetimes of high-quality n-GaAs heteroepitaxial thin films grown on vicinal Si(100) substrates by atomic hydrogen-assisted low-temperature molecular beam epitaxy (MBE) technique have been investigated. Photoluminescence decay characteristics have been evaluated and a minority carrier lifetime of as high as 8.0 ns has been successfully obtained, which is the highest value reported to date. These results are regarded as of particular importance for high-performance optoelectronic device applications especially for tandem solar cells.

Carbon nanotube via interconnects with large current carrying capacity

We fabricated a carbon nanotube (CNT) via interconnect and evaluated its electrical properties. We found that the CNT via resistance was independent of temperatures, which suggests that the carrier transport is ballistic. From the via height dependence of the resistance, the electron mean free path was estimated to be about 80 nm, which is similar to the via height predicted for hp32-nm technology node. This indicates that it will be possible to realize CNT vias with ballistic transport for hp32-nm technology node and below. It was also found that a CNT via was able to sustain a current density as high as 5.0 × 106 A/cm2 at 105 °C for 100 hours without any deterioration.

Fabrication of Graphene Directly on SiO2 without Transfer Processes by Annealing Sputtered Amorphous Carbon

We fabricated multilayer graphene directly on SiO2 by annealing sputtered amorphous carbon with a catalyst – a simple non-chemical vapor deposition method – without the use of complicated transfer processes. Structural analysis revealed that the graphene sheets formed an epitaxial structure aligned to the Co(111) surface between the Co catalyst and SiO2 dielectric. In the multilayer graphene, a resistivity of approximately 500 µΩ cm was obtained, which is one order of magnitude higher than that of highly oriented pyrolytic graphite.

Optimization Vector Quantization by Adaptive Associative-Memory-Based Codebook Learning in Combination with Huffman Coding

In the presented research on codebook optimization for vector quantization, an associative memory architecture is applied, which searches the most similar data among previously stored reference data. For realizing the learning function of new codebook data, a learning algorithm is implemented, which is based on this associative memory and which imitates the concept of the human short/long-term memory. The quality improvement of the codebook for vector quantization, created with the proposed learning algorithm, and the learning-parameter dependence of the improvement is evaluated with the Peak Signal Noise Ratio (PSNR), which is an index of the image quality. A quantitative PSNR improvement of 2.5 – 3.0 dB could be verified. Since the learning algorithm orders the codebook elements according to their usage frequency for the vector-quantization process, Huffman coding is additionally applied, and is verified to further improve the compression ratio from 12.8 to 14.1.

Carbon nanotube via technologies for advanced interconnect integration

We developed planar carbon nanotube (CNT) vias and their low-temperature fabrication processes consisting of low-temperature CNT growth and chemical mechanical polishing (CMP) of the CNT bundles. We were able to lower the CNT growth temperature to 400°C, which meets the requirement to avoid thermal damage to LSIs. Not only was the CMP effective for planarization; it also lowered the via resistance by about 25% with improved distribution. Our low-temperature planar CNT via technologies are very promising for the achievement of low-resistance scaled-down CNT vias for future LSI interconnects.