Daiyu Kondo

Electrical Properties of Carbon Nanotube Bundles for Future Via Interconnects

We have developed carbon nanotube (CNT) vias consisting of about 1000 tubes using thermal chemical vapor deposition (CVD) at a growth temperature of 450°C with cobalt catalysts, titanium carbide ohmic contacts, and tantalum barrier layers on copper wiring. The lowest resistance obtained was about 5 Ω/via. The total resistance of the CNT via was three orders of magnitude lower than that of one CNT, indicating that the current flows in parallel through about 1000 tubes. No degradation was observed for 100 hours at via current densities of 2×106 A/cm2, which is favorably compared with Cu vias.

Self-organization of Novel Carbon Composite Structure: Graphene Multi-Layers Combined Perpendicularly with Aligned Carbon Nanotubes

A novel carbon composite structure consisiting of graphene multi-layers and aligned multi-walled carbon nanotubes (MWNTs) has been discovered. The composite structure, which was synthesized by chemical vapor deposition, has graphene multi-layers combined with the upper ends of vertically aligned MWNTs on a substrate. This microscopically-combined structure has been confirmed by transmission electron microscopy. The substrate with the new structure looks gray and shiny, which is completely different from the appearance of a substrate with the usual vertically-aligned MWNTs. The new composite structure is expected to have excellent electrical and thermal properties, and therefore is likely to find many applications in electronics.

Low-Temperature Synthesis of Graphene and Fabrication of Top-Gated Field Effect Transistors without Using Transfer Processes

Thickness-controlled growth of few-layer and multi-layer graphene was performed at 650 °C by thermal chemical vapor deposition, and top-gated field effect transistors (FETs) were fabricated directly on a large SiO2/Si substrate without graphene-transfer processes. Graphene was synthesized on patterned Fe films. The iron was subsequently etched after both ends of the graphene were fixed by source and drain electrodes, leaving the graphene channels bridging the electrodes all over the substrate. Top-gated FETs were then made after covering the channels with HfO2. The fabricated devices exhibit ambipolar behavior and can sustain a high-density current. The growth mechanism of graphene was also investigated.

Novel approach to fabricating carbon nanotube via interconnects using size-controlled catalyst nanoparticles

We propose a new approach to fabricating carbon nanotube (CNT) vias, which uses preformed catalyst nanoparticles to grow CNTs. A newly-designed impactor provided size-classified catalyst particles, and a new deposition system injected them into via holes down to 40 nm in diameter. The resultant CNT-via resistance was 0.59 Omega for 2-mum vias, which is the lowest ever reported, improved from the previous studies using catalyst films. The improvement resulted from higher-density CNTs grown in the via holes by employing the nanoparticle catalyst

Carbon Nanotube Growth Technologies Using Tantalum Barrier Layer for Future ULSIs with Cu/Low-k Interconnect Processes

We succeeded in developing carbon nanotube (CNT) vias specifically adapted for the copper interconnect process used in ultra large-scale integrated circuits. The CNTs were grown selectively on titanium films using Co catalyst films. The use of tantalum enabled CNTs to be grown on Cu lines and prevented any increase in the sheet resistance of the Cu lines. A Cu wire/CNT via/Cu wire structure was fabricated and low resistance of the via was demonstrated. In addition, tests showed that a high current density of about 106 A/cm2 flowed into the CNT via for 125 hours.

Carbon nanotube bumps for LSI interconnect

We demonstrate, for the first time, carbon nanotube (CNT) flip chip bumps for LSI modules. The CNT bump is composed of a bundle of multi-walled CNTs. Resilient and flexible CNT bumps make flip chip LSI modules resistant to thermal stress. Furthermore, CNT bumps have a low electrical resistance and robustness over electromigration. In the experiment, the CNT bumps were used to connect a test evaluation group (TEG) chip and a host substrate, and their electrical resistance was evaluated. We found that the electrical contacts of CNT bumps with the chip and the substrate are important. For a good electrical contact, the CNT bumps were coated with gold and fixed to the chip and substrate. The resultant CNT bump with a diameter of 170 mum and a height of 100 mum exhibited a low resistance of 2.3 Omega. We then evaluated the flexibility of CNT bumps by pressing the TEG chip and measuring the displacement. The displacement between the TEG chip and host substrate was 10-20% of the bump height, demonstrating an excellent flexibility.

Thermal and source bumps utilizing carbon nanotubes for flip-chip high power amplifiers

Carbon nanotubes (CNTs) have been successfully developed as thermal and source bumps for flip-chip high power amplifiers (HPAs). The newly developed 15 mum long CNT bumps exhibit thermal conductivity of 1400 W/m-K. A flip-chip AlGaN/GaN HEMT HPA with a gate width of 2.4 mm utilizing CNT bumps, operating voltage of 40 V, exhibits an output power of 39 dBm at, a frequency of 2.1 GHz without any degradation due to heat-up. To our knowledge, this is the first report about, a practical application of CNTs using their high thermal conductivity

Low-resistance multi-walled carbon nanotube vias with parallel channel conduction of inner shells [IC interconnect applications]

We have succeeded in lowering the resistance of multi-walled carbon nanotube (MWNT) vias, using parallel channel conduction of each tubes inner shells. By optimizing the structure of the interface between MWNTs and Ti bottom contact layers, we could obtain a via resistance of 0.7 /spl Omega/ for a 2-/spl mu/m-diameter via consisting of about 1000 MWNTs. The corresponding resistance of about 0.7 k/spl Omega/ per MWNT indicates that most of the inner shells contribute to carrier conduction as an additional channel. The total resistance of the CNT vias that we fabricated is in the same order of magnitude as the theoretical value of W plugs and one order of magnitude higher than the theoretical value of Cu vias.

Robustness of CNT Via Interconnect Fabricated by Low Temperature Process over a High-Density Current

We fabricated a carbon nanotube (CNT) via interconnect and evaluated its robustness over a high-density current. CNTs were synthesized at temperatures as low as 365 °C, which is probably the lowest for this application, without degrading the ultra low-k interlayer dielectrics (k = 2.6). We measured the electrical properties of CNT vias as small as 160 nm in diameter and found that a CNT via was able to sustain a current density as high as 5.0×106 A/cm2 at 105 °C for 100 hours without any deterioration in its properties.

Electrical Properties of Carbon Nanotube Via Interconnects Fabricated by Novel Damascene Process

We studied the electrical properties of a carbon nanotube (CNT) via interconnect fabricated by a novel damascene process which is mostly compatible with conventional Cu interconnects. It was found that the resistance of 60-nm-height vias was independent of temperatures as high as 423 K, which suggests that the carrier transport is ballistic. The obtained resistance of 0.05 Omega for 2.8-mum-diameter vias is the lowest value ever reported. From the via height dependence of the resistance, the electron mean free path was estimated to be about 80 nm, which is similar to the via height predicted for 32-nm technology node (year 2013). This indicates that it will be possible to realize CNT vias with ballistic transport for 32-nm technology node and below.